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Электронный компонент: ICS843004I

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843004AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 11, 2005
1
Integrated
Circuit
Systems, Inc.
ICS843004I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS843004I is a 4 output LVPECL synthesizer
optimized to generate Fibre Channel reference
clock frequencies and is a member of the
HiPerClocks
TM
family of high performance clock
solutions from ICS. Using a 26.5625MHz 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz,
and 53.125MHz. The ICS843004I uses ICS' 3
rd
generation low
phase noise VCO technology and can achieve 1ps or lower
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS843004I is packaged in a small 24-pin
TSSOP package.
F
EATURES
Four 3.3V LVPECL outputs
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, 53.125MHz
VCO range: 560MHz - 680MHz
Output skew: 50ps (maximum)
RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(2.55MHz - 20MHz): 0.47ps (typical)
Full 3.3V or 2.5V supply modes
-40C to 85C ambient operating temperature
Lead-Free fully RoHS compliant
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
1
1
0
1
0
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
M = 24 (fixed)
F_SEL[1:0]
0 0 3
0 1 4
1 0 6
1 1 12
2
OSC
ICS843004I
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
nQ1
Q1
V
CC
o
Q0
nQ0
MR
nPLL_SEL
nc
V
CCA
F_SEL0
V
CC
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
nQ2
Q2
V
CCO
Q3
nQ3
V
EE
nc
nXTAL_SEL
TEST_CLK
V
EE
XTAL_IN
XTAL_OUT
24
23
22
21
20
19
18
17
16
15
14
13
B
LOCK
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IAGRAM
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MR
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Q2
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Q3
nQ3
Pulldown
Pulldown
26.5625MHz
Pulldown
Pulldown
Pulldown
843004AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 11, 2005
2
Integrated
Circuit
Systems, Inc.
ICS843004I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
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843004AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 11, 2005
3
Integrated
Circuit
Systems, Inc.
ICS843004I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = -40C
TO
85C
T
ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%
OR
2.5V5%, TA = -40C
TO
85C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
70C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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-
A
843004AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 11, 2005
4
Integrated
Circuit
Systems, Inc.
ICS843004I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
5A. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = -40C
TO
85C
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
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HARACTERISTICS
,
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CC
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CCA
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CCO
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OR
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TO
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-
843004AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 11, 2005
5
Integrated
Circuit
Systems, Inc.
ICS843004I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
5B. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 2.5V5%, TA = -40C
TO
85C
l
o
b
m
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S
r
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843004AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 11, 2005
6
Integrated
Circuit
Systems, Inc.
ICS843004I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
T
YPICAL
P
HASE
N
OISE
AT
53.125MH
Z
A
T
3.3V
53.125MHz
RMS Phase Jitter (Random)
637Khz to 5MHz = 0.49ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
Fibre Channel Jitter Filter
Phase Noise Result by adding
Fibre Channel Filter to raw data
Raw Phase Noise Data
dBc
Hz
N
OISE
P
O
WER
T
YPICAL
P
HASE
N
OISE
AT
212.5MH
Z
A
T
3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
212.5MHz
RMS Phase Jitter (Random)
2.55Mhz to 20MHz = 0.47ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
100
1k
10k
100k
1M
10M
100M
Fibre Channel Jitter Filter
Phase Noise Result by adding
Fibre Channel Filter to raw data
Raw Phase Noise Data
dBc
Hz
N
OISE
P
O
WER
843004AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 11, 2005
7
Integrated
Circuit
Systems, Inc.
ICS843004I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
R
ISE
/F
ALL
T
IME
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.33V
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
V
CC
,
V
CCA
, V
CCO
V
EE
t
sk(o)
Qy
Qx
nQy
nQx
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
Q0:Q3
nQ0:nQ3
RMS P
HASE
J
ITTER
O
UTPUT
S
KEW
SCOPE
Qx
nQx
LVPECL
2V
-0.5V 0.125V
V
CC
,
V
CCA
, V
CCO
V
EE
843004AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 11, 2005
8
Integrated
Circuit
Systems, Inc.
ICS843004I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843004I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V or 2.5V
.01
F
V
CC
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
designed to drive 50
transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion.
Figures 2A and
2B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.
843004AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 11, 2005
9
Integrated
Circuit
Systems, Inc.
ICS843004I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843004I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in
Figure 4
Figure 4. C
RYSTAL
I
NPU
t I
NTERFACE
below were determined using a 26.5625MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
ICS843004I
C1
33p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50
to V
CC
- 2V. For V
CCO
= 2.5V, the V
CCO
- 2V is very close to
ground level. The R3 in Figure 3B can be eliminated and the
termination is shown in
Figure 3C.
F
IGURE
3C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driv er
F
IGURE
3B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driv er
Zo = 50 Ohm
+
-
2.5V
F
IGURE
3A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driv er
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
843004AGI
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REV. A FEBRUARY 11, 2005
10
Integrated
Circuit
Systems, Inc.
ICS843004I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
L
AYOUT
G
UIDELINE
Figure 5 shows a schematic example of the ICS843004I. An
example of LVEPCL termination is shown in this schematic. Ad-
ditional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18pF
F
IGURE
5. ICS843004I S
CHEMATIC
E
XAMPLE
parallel resonant 26.5625MHz crystal is used. The C1=27pF
and C2=33pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 may be slightly adjusted
for optimizing frequency accuracy.
VCC=3.3V
C3
10uF
+
-
VCCO=3.3V
R3
133
To Logic
Input
pins
3.3V
VCC
Zo = 50 Ohm
Set Logic
Input to
'0'
C7
0.1u
3.3V
RD2
1K
VCC
VDD
VC
C
R10
82.5
R4
82.5
VCCA
Logic Control Input Examples
VDD
C2
33pF
C4
0.01u
+
-
Zo = 50 Ohm
RD1
Not Install
Zo = 50 Ohm
RU2
Not Install
R7
133
R8
82.5
C9
0.1u
C1
27pF
Set Logic
Input to
'1'
R9
133
X1
26.5625MHz
R2
10
18pF
To Logic
Input
pins
Zo = 50 Ohm
VCCO
R6
82.5
C6
0.1u
U1
ICS843004
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
nQ
1
Q1
VC
C
O
Q0
nQ
0
MR
nPLL_SE
L
NC
VC
C
A
F_
S
E
L
0
VC
C
F_
S
E
L
1
X
T
AL_O
U
T
X
T
AL_I
N
VE
E
T
EST
_C
LK
nX
T
A
L_SE
L
VC
C
VE
E
nQ
3
Q3
VC
C
O
Q2
nQ
2
C8
0.1u
R5
133
RU1
1K
VC
C
O
843004AGI
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REV. A FEBRUARY 11, 2005
11
Integrated
Circuit
Systems, Inc.
ICS843004I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843004I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843004I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 130mA = 450.45mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power
_MAX
(3.465V, with all outputs switching) = 450.45mW + 120mW = 570.45mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.571W * 65C/W = 122.1C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
ABLE
6. T
HERMAL
R
ESISTANCE


JA
FOR
24-
PIN
TSSOP, F
ORCED
C
ONVECTION


JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
843004AGI
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REV. A FEBRUARY 11, 2005
12
Integrated
Circuit
Systems, Inc.
ICS843004I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
6. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
843004AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 11, 2005
13
Integrated
Circuit
Systems, Inc.
ICS843004I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843004I is: 2578
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
TSSOP


JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
843004AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 11, 2005
14
Integrated
Circuit
Systems, Inc.
ICS843004I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
24 L
EAD
TSSOP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
S
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843004AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 11, 2005
15
Integrated
Circuit
Systems, Inc.
ICS843004I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM and F
EMTO
C
LOCKS
TM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.