Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Functional Description
- Parallel & Serial Load Operations Diagram
- Pin Descriptions
- Pin Characteristics
- Parallel & Serial Mode Function Table
- Programmable VCO Frequency Function Table
- Programmable Output Divider Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- LVPECL DC Characteristics
- Input Frequency Characteristics
- AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Output Skew Diagram
- Output Rise/Fall Time Diagram
- Cycle-to-Cycle Jitter Diagram
- Period Jitter Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Application Information
- Power Supply Filtering Techniques
- Power Supply Filtering Diagram
- Termination for LVPECL Outputs
- LVPECL Output Termination Diagrams
- Wiring the Differential Input to Accept Single Ended Levels
- Differential Clock Input Interface
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MH
Z
, L
OW
J
ITTER
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS8430-111 is a general purpose, dual out-
put high frequency synthesizer and a member of
the HiPerClockSTM family of High Performance
Clock Solutions from ICS. The CLK, nCLK pair
can accept most standard differential input lev-
els. The single ended TEST_CLK input accepts LVCMOS or
LVTTL input levels and translates them to 3.3V LVPECL levels.
The VCO operates at a frequency range of 200MHz to 700MHz.
With the output configured to divide the VCO frequency by 2,
output frequency steps as small as 2MHz can be achieved
using a 16MHz differential or single ended reference clock. Out-
put frequencies up to 700MHz can be programmed using the
serial or parallel interfaces to the configuration logic. The low
jitter and frequency range of the ICS8430-111 makes it an ideal
clock generator for most clock tree applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Dual differential 3.3V LVPECL output
Selectable 14MHz to 27MHz differential CLK, nCLK
or TEST_CLK input
CLK, nCLK accepts any differential input signal:
LVPECL, LVHSTL, LVDS, SSTL, HCSL
TEST_CLK accepts the following input types:
LVCMOS, LVTTL
Output frequency range up to 700MHz
VCO range: 200MHz to 700MHz
Parallel or serial interface for programming counter
and output dividers
Cycle-to-cycle jitter: 25ps (maximum)
3.3V supply voltage
0C to 70C ambient operating temperature
Industrial termperature information available upon request
VCO_SEL
CLK_SEL
TEST_CLK
CLK
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N2
VCO
PLL
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
N
CONFIGURATION
INTERFACE
LOGIC
M
0
1
0
1
16
PHASE DETECTOR
2
HiPerClockSTM
ICS
nCLK
MR
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CLK
TEST_CLK
CLK_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N 0
N 1
N 2
V
EE
V
EE
nFOUT0
FOUT0
V
CCO
nFOUT1
FOUT1
V
CC
TEST
nCLK
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8430-111
8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
2
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MH
Z
, L
OW
J
ITTER
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
the parallel input mode. The relationship between the VCO fre-
quency, the input frequency and the M divider is defined as
follows:
The M value and the required values of M0 through M8 are
shown in
Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
16MHz reference are defined as 100
M 350. The frequency
out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output divider
when S_LOAD transitions from LOW-to-HIGH. The M divide
and N output divide values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH, data at the
S_DATA input is passed directly to the M divider and N output
divider on each rising edge of S_CLOCK. The serial mode can
be used to program the M and N bits and test bits T1 and T0.
The internal registers T0 and T1 determine the state of the
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
t
S
t
H
t
S
t
H
t
S
M, N
F
UNCTIONAL
D
ESCRIPTION
The ICS8430-111 features a fully integrated PLL and there-
fore requires no external components for setting the loop
bandwidth. A differential clock input is used as the input to the
on-chip oscillator. The output of the oscillator is divided by 16
prior to the phase detector. A16MHz clock input provides a
1MHz reference frequency. The VCO of the PLL operates over
a range of 200 to 700MHz. The output of the M divider is also
applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by adjust-
ing the VCO control voltage. Note that for some values of M
(either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
each of the LVPECL output buffers. The divider provides a
50% output duty cycle.
The programmable features of the ICS8430-111 support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial.
Fig-
ure 1 shows the timing diagram for each mode. In
parallel mode the nP_LOAD input is initially LOW. The data on
inputs M0 through M8 and N0 through N2 is passed directly
to the M divider and N output divider. On the LOW-to-HIGH
transition of the nP_LOAD input, the data is latched and the M
divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M
and N bits can be hardwired to set the M divider and N output
divider to a specific default state that will automatically occur
during power-up. The TEST output is LOW when operating in
fVCO = f
IN
x M
T1
T0
TEST Output
0
0
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
1
CMOS Fout
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
*NOTE:
The NULL timing slot must be observed.
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
S_LOAD
fOUT = fVCO = f
IN
x M
N
N
8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
3
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MH
Z
, L
OW
J
ITTER
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
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8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
4
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MH
Z
, L
OW
J
ITTER
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3B. P
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VCO F
REQUENCY
F
UNCTION
T
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(NOTE 1)
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8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
5
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MH
Z
, L
OW
J
ITTER
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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2
/
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, V
O
-0.5V to V
CCO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
6
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MH
Z
, L
OW
J
ITTER
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
7
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MH
Z
, L
OW
J
ITTER
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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M
8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
8
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MH
Z
, L
OW
J
ITTER
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
R
ISE
/F
ALL
T
IME
C
YCLE
-
TO
-C
YCLE
J
ITTER
P
ERIOD
J
ITTER
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
S
KEW
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
SCOPE
Qx
nQx
LVPECL
V
CC
, V
CCA
, V
CCO
= 2V
V
EE
= -1.3V 0.165V
V
CMR
Cross Points
V
PP
V
CC
V
EE
CLK
nCLK
tsk(o)
nFOUTx
FOUTx
nFOUTy
FOUTy
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
FOUTx
nFOUTx
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
FOUTx
nFOUTx
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
contains 68.26% of all measurements
2
contains 95.4% of all measurements
3
contains 99.73% of all measurements
4
contains 99.99366% of all measurements
6
contains (100-1.973x10
-7
)% of all measurements
Histogram
8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
9
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MH
Z
, L
OW
J
ITTER
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8430-111 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
V
CC
- 2V
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. There are a few simple termination schemes.
Figures 3A and 3B show two different layouts which are recom-
mended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
10
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MH
Z
, L
OW
J
ITTER
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
Figure 4 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
4. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VCC
8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
11
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MH
Z
, L
OW
J
ITTER
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
F
IGURE
5C. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
5B. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
5D. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 5A to 5E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
5A. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 5A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
F
IGURE
5E. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
12
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MH
Z
, L
OW
J
ITTER
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8430-111.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8430-111 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 120mA = 415.8mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power
_MAX
(3.465V, with all outputs switching) = 415.8mW + 60mW = 475.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.476W * 42.1C/W = 90C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
7. T
HERMAL
R
ESISTANCE
JA
FOR
32-
PIN
LQFP, F
ORCED
C
ONVECTION
8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
13
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MH
Z
, L
OW
J
ITTER
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
) * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
6. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
14
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MH
Z
, L
OW
J
ITTER
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8430-111 is: 3960
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
15
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MH
Z
, L
OW
J
ITTER
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EAD
LQFP
T
ABLE
9. P
ACKAGE
D
IMENSIONS
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
3
A
0
6
.
1
1
A
5
0
.
0
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
9
0
.
0
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
0
6
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
0
6
.
5
e
C
I
S
A
B
0
8
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
q
0
7
c
c
c
0
1
.
0
Reference Document: JEDEC Publication 95, MS-026
8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
16
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MH
Z
, L
OW
J
ITTER
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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