Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Functional Description
- Parallel & Serial Load Operations Diagram
- Pin Descriptions
- Pin Characteristics
- Parallel & Serial Mode Function Table
- Programmable VCO 1 Frequency Function Table
- Programmable VCO 4 Frequency Function Table
- Programmable VCO 8Frequency Function Table
- Programmable Output Divider Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Input Frequency Characteristics
- Crystal Characteristics
- AC Characteristics
- Typical Phase Noise Plot
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Termination for LVPECL Outputs
- Layout Guideline
- Schematic of Recommended Layout
- Power & Grounding
- Clock Traces & Termination
- Crystal
- PCB Board Layout
- Power Consideraitons
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
1
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS843020-01 is a general purpose, dual out-
put Crystal-to-3.3V Differential LVPECL High Fre-
quency Synthesizer and a member of the
FemtoClocksTM family of High Performance Clock
Solutions from ICS. The ICS843020-01 is based
on ICS' 3
rd
generation VCO technology and is capable of sub-
1ps RMS Phase Jitter performance, making it ideal for use in
10 Gigabit Ethernet, 10 Gigabit Fibre Channel, SONET and
Serial ATA applications.
The ICS843020-01 is a highly flexible programmable synthe-
sizer capable of generating output frequencies over a range of
70MHz to 680MHz. The output frequency can be programmed
in small step sizes as low as 250
kHz when using a 16MHz
crystal,
8 input divider, and output divider = 8.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Dual differential 3.3V LVPECL outputs
Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
Output frequency range: 70MHz to 680MHz
Crystal input frequency range: 12MHz to 32MHz
VCO range: 560MHz to 680MHz
Parallel or serial interface for programming feedback
and output dividers
Input P_DIV under parallel load control
RMS phase jitter at 156.25MHz (1.875MHz to 20MHz):
0.49ps (typical), P_DIV =
1
3.3V supply voltage
0C to 70C ambient operating temperature
Lead-Free package fully RoHS compliant
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL_OUT
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N 0
N 1
P_DIV
V
EE
V
EE
nFOUT0
FOUT0
V
CCO
nFOUT1
FOUT1
V
CC
TEST
XT
AL_IN
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS843020-01
HiPerClockSTM
ICS
OSC
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
P_DIV
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
VCO
PLL
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
CONFIGURATION
INTERFACE
LOGIC
M
0
1
0
1
PHASE DETECTOR
MR
1
2
4
8
0
8
Float
1
(default)
1
4
N
P
843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
2
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS843020-01 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 560MHz to 680MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The ICS843020-01 supports either serial or parallel program-
ming modes to program the M feedback divider and N output
divider. The input divider P can only be changed using the P_DIV
pin. It cannot be changed from the default
1 setting using the
serial interface.
Figure 1 shows the timing diagram for each mode.
In parallel mode, the nP_LOAD input is initially LOW. The data
on inputs M0 through M8 and N0 and N1 is passed directly to
the M divider and N output divider. On the LOW-to-HIGH transi-
tion of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and N bits can be
hardwired to set the M divider and N output divider to a specific
default state that will automatically occur during power-up. The
TEST output is LOW when operating in the parallel input mode.
The relation-ship between the VCO frequency, the crystal fre-
quency and the M divider is defined as follows:
The M value and the required values of M0 through M8 are
shown in Table 3B to program the VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 23
M 27 (P = 1). The
frequency out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-to-
LOW transition of S_LOAD. If S_LOAD is held HIGH, data at
the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
F
UNCTIONAL
D
ESCRIPTION
T1
T0
TEST Output
0
0
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
1
CMOS Fout
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
*NOTE: The NULL timing slot must be observed.
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
M, N, P
t
S
t
H
t
S
t
H
t
S
T 1
T0
*NULL
N 1
N 0
M8
M7
M6
M5
M4
M3
M2
M1
M 0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1, P_DIV
nP_LOAD
fVCO = fxtal x M
P
FOUT = fVCO = fxtal x M
N
N x P
843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
3
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
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843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
4
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
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3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
WITH
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1 (P_DIV = F
LOAT
)
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H
M
5
2
f
o
T
ABLE
3C. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
WITH
P =
4 (P_DIV = 1)
y
c
n
e
u
q
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r
F
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C
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)
z
H
M
(
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3
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1
8
4
2
1
8
M
7
M
6
M
5
M
4
M
3
M
2
M
1
M
0
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5
7
5
2
9
0
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5
2
f
o
843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
5
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3E. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
s
t
u
p
n
I
e
u
l
a
V
r
e
d
i
v
i
D
N
)
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H
M
(
y
c
n
e
u
q
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r
F
t
u
p
t
u
O
1
N
0
N
m
u
m
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n
i
M
m
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m
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x
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M
0
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0
6
5
0
8
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8
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4
3
1
0
4
0
4
1
0
7
1
1
1
8
0
7
5
8
T
ABLE
3D. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
WITH
P =
8 (P_DIV = 0)
y
c
n
e
u
q
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r
F
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C
V
)
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H
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(
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7
M
6
M
5
M
4
M
3
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2
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1
M
0
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5
7
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5
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843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
6
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
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t
e
m
a
r
a
P
s
n
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t
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m
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5
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1
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3
3
.
3
5
6
4
.
3
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a
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0
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1
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C
C
t
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p
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g
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p
p
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S
t
u
p
t
u
O
4
1
A
m
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, V
O
(LVCMOS)
-0.5V to V
DDO
+ 0.5V
Outputs, I
O
(LVPECL)
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
7
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
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t
i
d
n
o
C
t
s
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T
m
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m
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M
l
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K
L
C
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T
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T
,
K
C
O
L
C
_
S
1
N
:
0
N
,
8
M
:
0
M
2
V
C
C
3
.
0
+
V
V
I
D
_
P
V
C
C
4
.
0
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V
L
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p
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l
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w
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L
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V
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A
T
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,
K
L
C
_
T
S
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,
K
C
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C
_
S
1
N
:
0
N
,
8
M
:
0
M
3
.
0
-
8
.
0
V
V
I
D
_
P
V
C
C
4
.
0
+
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V
M
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d
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V
NOTE 1: Outputs terminated with 50
to V
CCO
/2.
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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"
843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
8
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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/
T
ABLE
7. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
9
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
YPICAL
P
HASE
N
OISE
AT
156.25MH
Z
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.49ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
Filter
Phase Noise Result by adding
a Filter to raw data
Raw Phase Noise Data
dBc
Hz
N
OISE
P
O
WER
843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
10
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
P
HASE
J
ITTER
O
UTPUT
S
KEW
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
-1.3V 0.165V
t
sk(o)
nFOUTx
FOUTx
nFOUTy
FOUTy
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
FOUTx
nFOUTx
V
CC
,
V
CCA
,
V
CCO
V
EE
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
11
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843020-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
C
RYSTAL
I
NPUT
I
NTERFACE
A crystal can be characterized for either series or parallel mode
operation. The ICS843020-01 has a built-in crystal oscillator circuit.
This interface can accept either a series or parallel crystal without
additional components and generate frequencies with accuracy
Figure 3. C
RYSTAL
I
NPU
t I
NTERFACE
suitable for most applications. Additional accuracy can be
achieved by adding two small capacitors C1 and C2 as shown in
Figure 3.
C1
18p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN
843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
12
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
4B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
4A. LVPECL O
UTPUT
T
ERMINATION
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
13
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
The schematic of the ICS843020-01 layout example used in
this layout guideline is shown in
Figure 5A. The ICS843020-
01 recommended PCB board layout for this example is shown
in
Figure 5B. This layout example is used as a general guide-
L
AYOUT
G
UIDELINE
F
IGURE
5A. S
CHEMATIC
OF
R
ECOMMENDED
L
AYOUT
line. The layout in the actual system will depend on the se-
lected component types, the density of the components, the
density of the traces, and the stack up of the P.C. board.
VC
C
C2
X1
Set Logic
Input to
'1'
'0'
C14
0.1u
S_LOAD
Set Logic
Input to
'0'
TL1
Zo = 50 Ohm
'1'
VCC
REF_IN
VCCA
RU1
1K
C15
0.1u
RU2
Not Install
VCC
C16
10u
To Logic
Input
pins
R7
10
C11
0.01u
RD1
Not Install
S_DATA
R3
133
C1
R1
133
R5
1K
U1
ICS843020-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
M5
M6
M7
M8
N0
N1
P_DIV
VEE
TE
S
T
VC
C
FO
U
T1
nF
O
U
T
1
V
CCO
FO
U
T0
nF
O
U
T
0
VE
E
MR
S_CLOCK
S_DATA
S_LOAD
VCCA
nXTAL_SEL
T_CLK
XTAL_O
M4
M3
M2
M1
M0
VC
O_SE
L
nP_LO
AD
XT
A
L
_
I
Float
VCC
FO
UTN
S_CLOCK
To Logic
Input
pins
RD2
1K
R2
82.5
VCC
Logic Input Pin Examples
XTAL_SEL
+
-
R6
1K
R4
82.5
TL2
Zo = 50 Ohm
VC
C
VCC
FO
UT
843020AY-01
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REV. B APRIL 14, 2005
14
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
F
IGURE
5B. PCB B
OARD
L
AYOUT
FOR
ICS843020-01
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C14 and C15, as close as pos-
sible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
CCA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have the
same length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
25 (XTAL_IN) and 24 (XTAL_OUT). The trace length between the
X1 and U1 should be kept to a minimum to avoid unwanted para-
sitic inductance and capacitance. Other signal traces should not
be routed near the crystal traces.
TL1, TL21N are 50 Ohm
traces and equal length
R2
VIA
T
L1N
GND
C15
R4
TL1
R1
TL
1
X1
VCC
C11
PIN 1
C1
C14
TL1N
C2
R3
C16
R7
Close to the input
pins of the
receiver
U1
VCCA
843020AY-01
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REV. B APRIL 14, 2005
15
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843020-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843020-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 180mA = 623.7mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power
_MAX
(3.465V, with all outputs switching) = 623.7mW + 60mW = 683.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.684W * 42.1C/W = 98.8C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
8. T
HERMAL
R
ESISTANCE
JA
FOR
32-
PIN
LQFP, F
ORCED
C
ONVECTION
843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
16
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
) * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
6. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
17
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843020-01 is: 5371
T
ABLE
9.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
18
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EAD
LQFP
T
ABLE
10. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
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843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
19
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
11. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
843020AY-01
www.icst.com/products/hiperclocks.html
REV. B APRIL 14, 2005
20
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
TM 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
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