8430252CG-45
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 9, 2005
1
Integrated
Circuit
Systems, Inc.
ICS8430252-45
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS8430252-45 is a 2 output LVPECL and
LVCMOS/LVTTL Synthesizer optimized to gen-
erate Ethernet reference clock frequencies and
is a member of the HiPerClocksTM family of high
performance clock solutions from ICS. Using a
25MHz, 18pF parallel resonant crystal, the following fre-
quencies can be generated: 156.25MHz LVPECL output
and, 125MHz LVCMOS output. The 8430252-45 uses ICS'
3rd generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter, easily meet-
ing Ethernet jitter requirements. The ICS8430252-45 is
packaged in a small 16-pin TSSOP package.
F
EATURES
One differential 3.3V LVPECL output and
One LVCMOS/LVTTL output
Crystal oscillator interface designed for a 25MHz,
18pF parallel resonant crystal
A 25MHz crystal generates both an output frequency of
156.25MHz (LVPECL) and 125MHz (LVCMOS)
VCO frequency: 625MHz
RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz) using
a 25MHz crystal: 0.39ps (typical)
Full 3.3V supply mode
0C to 70C ambient operating temperature
Industrial temperature available upon request
Available in both standard and lead-free RoHS compliant
packages
HiPerClockSTM
ICS
B
LOCK
D
IAGRAM
XTAL_IN
XTAL_OUT
QA
QB
nQB
P
IN
A
SSIGNMENT
OE
V
EE
QA
V
CCO
_
A
nc
nc
V
CCA
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK_EN
V
EE
QB
nQB
V
CCO
_
B
XTAL_IN
XTAL_OUT
V
EE
ICS8430252-45
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
OSC
Phase
Detector
VCO
625MHz
Feedback Divider
25
4
5
25MHz
CLK_EN
OE
Pullup
Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8430252CG-45
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 9, 2005
2
Integrated
Circuit
Systems, Inc.
ICS8430252-45
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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8430252CG-45
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 9, 2005
3
Integrated
Circuit
Systems, Inc.
ICS8430252-45
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A,
V
CCO_B
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= 3.3V5%, T
A
= 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
89C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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HARACTERISTICS
,
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CC
= V
CCA
= V
CCO_B
= 3.3V5%, T
A
= 0C
TO
70C
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8430252CG-45
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 9, 2005
4
Integrated
Circuit
Systems, Inc.
ICS8430252-45
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A,
V
CCO_B
= 3.3V5%, TA = 0C
TO
70C
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
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Q
0
5
%
B
Q
n
,
B
Q
0
5
%
.
s
t
o
l
P
e
s
i
o
N
e
s
a
h
P
e
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o
t
r
e
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a
e
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P
:
1
E
T
O
N
8430252CG-45
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 9, 2005
5
Integrated
Circuit
Systems, Inc.
ICS8430252-45
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
156.25MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.39ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
Phase Noise Result by adding
10Gb Ethernet Filterto raw data
Raw Phase Noise Data
dBc
Hz
N
OISE
P
O
WER
T
YPICAL
P
HASE
N
OISE
AT
156.25MH
Z
10Gb Ethernet Filter
8430252CG-45
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 9, 2005
6
Integrated
Circuit
Systems, Inc.
ICS8430252-45
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
QB
RMS P
HASE
J
ITTER
3.3V C
ORE
/3.3V LVCMOS O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/3.3V LVPECL O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V0.165V
LVCMOS O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
V
CC
,
V
CCA
, V
CCO_B
V
EE
nQB
LVPECL O
UTPUT
R
ISE
/F
ALL
T
IME
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
e
r
SCOPE
Qx
LVCMOS
1.65V5%
-1.65V5%
V
CC
,
V
CCA
, V
CCO_A
V
EE
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
V
CCO_LVCMOS
2
t
PW
QA
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
LVPECL O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
LVCMOS O
UTPUT
R
ISE
/F
ALL
T
IME
8430252CG-45
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 9, 2005
7
Integrated
Circuit
Systems, Inc.
ICS8430252-45
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
A
PPLICATION
I
NFORMATION
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS8430252-45 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2
below were determined using a 25MHz, 18pF
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
parallel resonant crystal and were chosen to minimize the
ppm error.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8430252-45 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO_X
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
pin.
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
C1
22p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN
8430252CG-45
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 9, 2005
8
Integrated
Circuit
Systems, Inc.
ICS8430252-45
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
designed to drive 50
transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion.
Figures 3A and
3B
show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.
I
NPUTS
:
S
ELECT
P
INS
:
All select pins have internal pull-ups and pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
8430252CG-45
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 9, 2005
9
Integrated
Circuit
Systems, Inc.
ICS8430252-45
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8430252-45.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8430252-45 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 75mA = 259.88mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 90mW
Total Power
_MAX
(3.465V, with all outputs switching) = 259.9mW + 60mW = 319.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.320W * 81.8C/W = 96.2C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
ABLE
7. T
HERMAL
R
ESISTANCE
JA
FOR
16-
PIN
TSSOP, F
ORCED
C
ONVECTION
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
137.1C/W
118.2C/W
106.8C/W
Multi-Layer PCB, JEDEC Standard Test Boards
89.0C/W
81.8C/W
78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8430252CG-45
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 9, 2005
10
Integrated
Circuit
Systems, Inc.
ICS8430252-45
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 4.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
4. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
8430252CG-45
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 9, 2005
11
Integrated
Circuit
Systems, Inc.
ICS8430252-45
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8430252-45 is: 2070
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
16 L
EAD
TSSOP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
137.1C/W
118.2C/W
106.8C/W
Multi-Layer PCB, JEDEC Standard Test Boards
89.0C/W
81.8C/W
78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8430252CG-45
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 9, 2005
12
Integrated
Circuit
Systems, Inc.
ICS8430252-45
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
16 L
EAD
TSSOP
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
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Y
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8430252CG-45
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 9, 2005
13
Integrated
Circuit
Systems, Inc.
ICS8430252-45
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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