Document Outline
- General Description
- Features
- Frequency Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Crystal Characteristics
- AC Characteristics
- Typical Phase Noise Plot at 312.5MHz
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- RMS Phase Jitter Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Output Rise/Fall Time Diagram
- Application Information
- Crystal Input Interface
- Termination for 3.3V LVPECL Output
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
843031AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2004
1
Integrated
Circuit
Systems, Inc.
ICS843031
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS843031 is a 1 Gigabit Ethernet Clock
Generator and a member of the HiPerClocks
TM
family of high performance devices from ICS. The
ICS843031 can synthesize 1 Gigabit Ethernet,
SONET, or Serial ATA reference clock frequencies
with the appropriate choice of crystal and output divider. The
ICS843031 has excellent phase jitter performance and is
packaged in a small 8-pin TSSOP, making it ideal for use in
systems with limited board space.
F
EATURES
1 differential 3.3V LVPECL output
Crystal oscillator interface designed for
18pF parallel resonant crystals
VCO frequency range: 580MHz - 700MHz
RMS phase jitter @312.5MHz (1.875MHz - 20MHz):
0.5ps (typical)
3.3V operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
HiPerClockSTM
ICS
ICS843031
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
V
CC
XTAL_OUT
XTAL_IN
V
EE
1
2
3
4
Q0
nQ0
V
CC
OE
8
7
6
5
OSC
Phase
Detector
VCO
24
(fixed)
2
XTAL_IN
XTAL-OUT
nQ0
Q0
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
REQUENCY
T
ABLE
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The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843031AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2004
2
Integrated
Circuit
Systems, Inc.
ICS843031
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
1. P
IN
D
ESCRIPTIONS
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843031AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2004
3
Integrated
Circuit
Systems, Inc.
ICS843031
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
=0C
TO
70C
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HARACTERISTICS
,
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CC
= 3.3V5%, T
A
=0C
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BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
101.7C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
=0C
TO
70C
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5. AC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
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=0C
TO
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843031AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2004
4
Integrated
Circuit
Systems, Inc.
ICS843031
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
AT
312.5MH
Z
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
312.5MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.50ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
dBc
Hz
N
OISE
P
O
WER
Phase Noise Result by adding 1
Gigabit Ethernet Filter to raw data
Raw Phase Noise Data
1 Gigabit Ethernet Filter
843031AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2004
5
Integrated
Circuit
Systems, Inc.
ICS843031
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.165V
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
Q0
nQ0
V
EE
V
CC
RMS P
HASE
J
ITTER
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under Offset Frequency Markers
Noise P
o
w
er
843031AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2004
6
Integrated
Circuit
Systems, Inc.
ICS843031
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
A
PPLICATION
I
NFORMATION
Figure 1. C
RYSTAL
I
NPU
t I
NTERFACE
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843031 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 1 below were determined using a 26.04167MHz, 18pF
parallel resonant crystal and were chosen to minimize the ppm
error. The optimum C1 and C2 values can be slightly adjusted
for different board layouts.
X1
18pF Parallel Cry stal
C1
12p
XTAL_OUT
XTAL_IN
C2
12p
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
drive 50
transmission lines.Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
843031AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2004
7
Integrated
Circuit
Systems, Inc.
ICS843031
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8430
31.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8430
31 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_TYP
= 3.465V * 65mA = 225.2mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power
_MAX
(3.465V, with all outputs switching) = 225.2mW + 30mW = 255.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.255W * 90.5C/W = 93.1C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
ABLE
6. T
HERMAL
R
ESISTANCE
JA
FOR
8-
PIN
TSSOP, F
ORCED
C
ONVECTION
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
843031AG
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REV. A NOVEMBER 29, 2004
8
Integrated
Circuit
Systems, Inc.
ICS843031
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 4.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
3. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
843031AG
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REV. A NOVEMBER 29, 2004
9
Integrated
Circuit
Systems, Inc.
ICS843031
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843031 is: 2360
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
843031AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2004
10
Integrated
Circuit
Systems, Inc.
ICS843031
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
8 L
EAD
TSSOP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
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Y
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r
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0
843031AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2004
11
Integrated
Circuit
Systems, Inc.
ICS843031
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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