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Электронный компонент: ICS843034AY-01T

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843034AY-01
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
1
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS843034-01 is a general purpose, low
phase noise LVPECL synthesizer which can
generate frequencies for a wide variety of
applications. The ICS843034-01 has a 4:1
input Multiplexer from which the following
inputs can be selected: 1 differential input, 1
single-ended input, or one of two crystal oscillators,
thus making the device ideal for frequency translation or
generation. Each differential LVPECL output pair has an
output divider which can be independently set so that two
different frequencies can be generated. Additionally, each
LVPECL output pair has a dedicated power supply pin so
the outputs can run at 3.3V or 2.5V. The ICS843034-01
also supplies a buffered copy of the reference clock or
crystal frequency on the single-ended REF_CLK pin which
can be enabled or disabled (disabled by default). The output
frequency can be programmed using either a serial or
parallel programming interface.
The ICS843034-01 has excellent <1ps phase jitter
performance over the 637kHz - 5MHz integration range, thus
making it suitable for use in Fibre Channel, SONET, and
Ethernet/1Gb Ethernet applications.
Example applications include systems which must support
both FEC and non FEC rates. In 10Gb Fibre Channel, for
example, you can use a 25.5MHz crystal to generate a
159.375MHz reference clock, and then switch to a
20.544MHz crystal to generate 164.355MHz for 66/64 FEC.
Other applications could include supporting both Ethernet
frequencies and SONET frequencies in an application. When
Ethernet frequencies are needed, a 25MHz crystal can be
used and when SONET frequencies are needed, the input
MUX can be switched to select a 38.88MHz Crystal.
F
EATURES
Dual differential 3.3V LVPECL outputs which can be set
independently for either 3.3V or 2.5V
4:1 Input Mux:
1 differential input
1 single-ended input
2 crystal oscillator interfaces
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
TEST_CLK accepts LVCMOS or LVTTL input levels
Output frequency range: 30.625MHz to 640MHz
Crystal input frequency range: 12MHz to 40MHz
VCO range: 490MHz to 640MHz
Parallel or serial interface for programming feedback divider
and output dividers
RMS phase jitter at 106.25MHz, using a 25.5MHz crystal
(637kHz to 5MHz): 0.61ps (typical)
Supply voltage modes:
LVPECL outputs (core/outputs):
3.3V/3.3V
3.3V/2.5V
REF_CLK output (core/outputs):
3.3V/3.3V
3.3V/2.5V
0C to 70C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
M8
NB0
NB1
NB2
OE_REF
OE_A
OE_B
V
CC
NA0
NA1
NA2
V
EE
XTAL_OUT1
XTAL_IN1
XTAL_OUT0
XTAL_IN0
TEST_CLK
SEL1
SEL0
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
CLK
nCLK
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
M5
M6
M7
ICS843034-01
48-Pin LQFP
7mm x 7mm x 1.4mm
package body
Y Package
Top View
V
EE
P_DIV
V
CCO
_
REF
REF_CLK
V
CCO
_
B
nFOUTB0
FOUTB0
V
CCO
_
A
nFOUT
A0
FOUT
A
0
V
CC
TEST
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843034AY-01
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
2
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
OSC
C
I
L
M
0
0
1
001
011
101
111
16
000
1
001
2
010
3
011
4
5
101
6
8
111
16
OSC
P
HASE
D
ETECTOR
VCO
0 0
0 1
1 0
1 1
1
4
0
8
FOUTA0
nFOUTA0
FOUTB0
nFOUTB0
REF_CLK
TEST
V
CCO_REF
V
CCO_A
V
CCO_B
OE_A
VCO_SEL
XTAL_IN0
XTAL_OUT0
XTAL_IN1
XTAL_OUT1
CLK
nCLK
TEST_CLK
SEL1
SEL0
P_DIV
OE_B
MR
OE_REF
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M8:M0
NA2:NA0
NB2:NB0
B
LOCK
D
IAGRAM
843034AY-01
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
3
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
Nx bits can be hardwired to set the M divider and Nx output
divider to a specific default state that will automatically occur
during power-up. The TEST output is LOW when operating in
the parallel input mode. The relationship between the VCO fre-
quency, the crystal frequency and the M divider is defined as
follows:
The M value and the required values of M0 through M5 are shown
in Table 3B to program the VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock for a 25MHz
reference are defined as 20
M 25. The frequency out is de-
fined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and Nx output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and Nx output divide values are latched on the HIGH-
to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data
at the S_DATA input is passed directly to the M divider and Nx
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and Nx bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS843034-01 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 490MHz to 640MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The ICS843034-01 supports either serial or parallel program-
ming modes to program the M feedback divider and N output
divider. The input divider P can only be changed using the P_DIV
pin. It cannot be changed from the default
1 setting using the
serial interface.
Figure 1
shows the timing diagram for each mode.
In parallel mode, the nP_LOAD input is initially LOW. The data
on the M, NA, and NB inputs are passed directly to the M di-
vider and both N output dividers. On the LOW-to-HIGH transi-
tion of the nP_LOAD input, the data is latched and the M and N
dividers remain loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M and
T1
T0
TEST Output
0
0
LOW
0
1
S_Data, Shift Register Output
1
0
Output of M divider
1
1
CMOS Fout A0
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
T 1
T0
NB2
NB1 NB0
NA2
NA1
NA0
M8
M7
M6
M5
M4
M3
M2
M1
M 0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, P_DIV,
NA0:NA2, NB0:NB2
nP_LOAD
fVCO = fxtal x M
P
FOUT = fVCO = fxtal x M
N
N x P
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
M, N, P
t
S
t
S
t
H
t
S
t
H
Time
S_LOAD
843034AY-01
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
4
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
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D
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843034AY-01
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
5
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
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LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
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843034AY-01
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
6
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
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LVPECL F
REQUENCY
S
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PRELIMINARY
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843034AY-01
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
7
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
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4A. P
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CC
= V
CCA
= 3.3V5%, V
CCO_A
= V
CCO_B
= 3.3V5%
OR
2.5V5%, T
A
= 0C
TO
70C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, V
O
(LVCMOS)
-0.5V to V
CCO
+ 0.5V
Outputs, I
O
(LVPECL)
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
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.
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.
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2
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.
2
V
843034AY-01
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
8
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO_A
= V
CCO_B
= 3.3V5%
OR
2.5V5%, T
A
= 0C
TO
70C)
NOTE 1: Output terminated with 50
to V
CCO_REF
/2.
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H
I
.
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO_A
= V
CCO_B
= 3.3V5%
OR
2.5V5%, T
A
= 0C
TO
70C
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V
843034AY-01
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
9
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, T
A
= 0C
TO
70C
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T
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T
ABLE
7A. AC C
HARACTERISTICS
,
V
CC
= V
CCA
=
V
CCO_A
= V
CCO_B
=
3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CCO_A
= V
CCO_B
=
2.375V
TO
3.465V, T
A
= 0C
TO
70C
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2
-
843034AY-01
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
10
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
7B. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%,
V
CCO_A
= V
CCO_B
=
2.5V5%, T
A
= 0C
TO
70C
T
ABLE
7C. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO_A
= 3.3V5%, V
CCO_B
= 2.5V5%,T
A
= 0C
TO
70C
OR
V
CC
= V
CCA
= 3.3V5%, V
CCO_A
= 2.5V5%, V
CCO_B
= 3.3V5%,T
A
= 0C
TO
70C
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843034AY-01
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
11
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
AT
106.25MH
Z
106.25MHz
RMS Phase Jitter (Random)
637kHz to 5MHz = 0.61ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
a Filter to raw data
Raw Phase Noise Data
Filter
843034AY-01
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
12
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
contains 68.26% of all measurements
2
contains 95.4% of all measurements
3
contains 99.73% of all measurements
4
contains 99.99366% of all measurements
6
contains (100-1.973x10
-7
)% of all measurements
Histogram
t
sk(o)
nFOUTx
FOUTx
nFOUTy
FOUTy
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V C
ORE
/2.5V REF_CLK O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
FOUTA0/nFOUTA0, FOUTB0/nFOUTB0
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.165V
V
CC
,
V
CCA
, V
CCO_A,
V
CCO_B
V
EE
3.3VC
ORE
/3.3V REF_CLK O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
FOUTA0/nFOUTA0, FOUTB0/nFOUTB0
SCOPE
Qx
nQx
LVPECL
2.8V0.04V
-0.5V 0.125V
V
CC
,
V
CCA
V
EE
V
CCO_A,
V
CCO_B
2V
SCOPE
Qx
LVCMOS
1.65V5%
-1.65V 5%
V
EE
O
UTPUT
S
KEW
P
ERIOD
J
ITTER
SCOPE
Qx
LVCMOS
2.05V0.04V
-1.25V 5%
1.25V5%
V
EE
V
CC
,
V
CCA
,
V
CCO_REF
V
CC
,
V
CCA
V
CCO_REF
843034AY-01
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
13
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
O
UTPUT
D
UTY
C
YCLE
/O
UTPUT
P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
FOUTA0
nFOUTA0
843034AY-01
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
14
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843034-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO_x
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2
illustrates how
a 24
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
24
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
A
PPLICATION
I
NFORMATION
Figure 3
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
LVCMOS/LVTTL L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VCC
F
IGURE
3. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
843034AY-01
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REV. C NOVEMBER 28, 2005
15
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
Figure 4. C
RYSTAL
I
NPU
t I
NTERFACE
ICS84332
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843034-01 has been characterized with 18pF paral-
lel resonant crystals. The capacitor values, C1 and C2, shown
in
Figure 4
below were determined using a 25MHz, 18pF
parallel resonant crystal and were chosen to minimize the
ppm error. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
ICS843034-01
C1
22p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN
F
IGURE
5C. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
5B. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
5D. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 5A to 5D show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
5A. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 5A,
the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
843034AY-01
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REV. C NOVEMBER 28, 2005
16
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUTx and nFOUTx are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
6B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
6A. LVPECL O
UTPUT
T
ERMINATION
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 6A and 6B
show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
resistor can be tied from XTAL_IN to ground.
CLK I
NPUT
:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the CLK input to
ground.
CLK/nCLK I
NPUT
:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
resistor can be tied from
CLK to ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
843034AY-01
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REV. C NOVEMBER 28, 2005
17
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 7A
and
Figure 7B
show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to ter-
minating 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very
close to ground level. The R3 in
Figure 7B
can be eliminated
and the termination is shown in
Figure 7C.
F
IGURE
7C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driv er
F
IGURE
7B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driv er
Zo = 50 Ohm
+
-
2.5V
F
IGURE
7A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driv er
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
843034AY-01
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REV. C NOVEMBER 28, 2005
18
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843034-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843034-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 185mA = 641mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power
_MAX
(3.465V, with all outputs switching) = 641mW + 60mW = 701mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.701W * 42.1C/W = 99.5C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).


JA
by Velocity (Linear Feet per Minute)
T
ABLE
8. T
HERMAL
R
ESISTANCE


JA
FOR
48-
PIN
LQFP, F
ORCED
C
ONVECTION
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843034AY-01
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REV. C NOVEMBER 28, 2005
19
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 8.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
8. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
843034AY-01
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REV. C NOVEMBER 28, 2005
20
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843034-01 is: 5084
T
ABLE
9.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
48 L
EAD
LQFP


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843034AY-01
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REV. C NOVEMBER 28, 2005
21
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
48 L
EAD
LQFP
T
ABLE
10. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
N
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843034AY-01
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REV. C NOVEMBER 28, 2005
22
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
TM
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
11. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
The aforementioned trademark, HiPerClockSTM and F
EMTO
C
LOCKS
TM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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