Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- 3.3V Power Supply DC Characteristics
- 2.5V Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- LVPECL DC Characteristics
- 3.3V AC Characteristics
- 2.5V AC Characteristics
- Typical Phase Noise Plots
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Termination for 3.3V LVPECL Output
- Termination for 2.5V LVPECL Output
- Power Considerations
- Power Dissipation
- Juntion Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
843081AGI-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 23, 2006
1
Integrated
Circuit
Systems, Inc.
ICS843081I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL C
LOCK
M
ULTIPLIER
G
ENERAL
D
ESCRIPTION
The ICS843081I-01 is an Ethernet Clock
Multiplier and a member of the HiPerClocks
TM
family of high performance devices from ICS. The
ICS843081I-01 accepts a crystal reference of
19.6MHz - 28MHz. The ICS843081I-01 has
excellent 1ps or lower phase jitter performance, over the
1.875MHz - 20MHz integration range. The ICS843081I-01 is
packaged in a small 8-pin TSSOP, making it ideal for use in
systems with limited board space.
F
EATURES
One differential LVPECL output
One crystal oscillator interface: 19.6MHz - 28MHz
Output frequency range: 490MHz - 700MHz
VCO range: 490MHz - 700MHz
RMS phase jitter @ 625MHz using a 25MHz reference
(1.875MHz - 20MHz): 0.32ps (typical)
3.3V or 2.5V operating supply
-40C to 85C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
HiPerClockSTM
ICS
ICS843081I-01
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
V
CCA
XTAL_OUT
XTAL_IN
V
EE
1
2
3
4
V
CC
Q
nQ
OE
8
7
6
5
VCO
490 - 700 MHz
Phase
Detector
M = 25 (fixed)
OE
XTAL_IN
XTAL_OUT
Q
nQ
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
REQUENCY
E
XAMPLE
F
UNCTION
T
ABLE
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0
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2
0
0
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5
2
5
2
5
2
6
8
2
5
2
0
0
7
843081AGI-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 23, 2006
2
Integrated
Circuit
Systems, Inc.
ICS843081I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL C
LOCK
M
ULTIPLIER
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
1. P
IN
D
ESCRIPTIONS
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843081AGI-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 23, 2006
3
Integrated
Circuit
Systems, Inc.
ICS843081I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL C
LOCK
M
ULTIPLIER
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V 5%, T
A
= -40C
TO
85C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
101.7C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V 5%
OR
2.5V 5%, T
A
= -40C
TO
85C
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 2.5V 5%, T
A
= -40C
TO
85C
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843081AGI-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 23, 2006
4
Integrated
Circuit
Systems, Inc.
ICS843081I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL C
LOCK
M
ULTIPLIER
T
ABLE
5A. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V 5%, T
A
= -40C
TO
85C
T
ABLE
5B. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= 2.5V 5%, T
A
= -40C
TO
85C
T
ABLE
3D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V 5%
OR
2.5V 5%, T
A
= -40C
TO
85C
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843081AGI-01
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REV. B JANUARY 23, 2006
5
Integrated
Circuit
Systems, Inc.
ICS843081I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL C
LOCK
M
ULTIPLIER
T
YPICAL
P
HASE
N
OISE
AT
625MH
Z
@ 3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
200
625MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.32ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
OWER
dBc
Hz
625MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.39ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
OWER
dBc
Hz
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
200
T
YPICAL
P
HASE
N
OISE
AT
625MH
Z
@ 2.5V
10
100
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
100M
Phase Noise Result by adding
a Gb Ethernet Filter to raw data
Raw Phase Noise Data
Gb Ethernet Filter
Phase Noise Result by adding
a Gb Ethernet Filter to raw data
Raw Phase Noise Data
Gb Ethernet Filter
843081AGI-01
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REV. B JANUARY 23, 2006
6
Integrated
Circuit
Systems, Inc.
ICS843081I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL C
LOCK
M
ULTIPLIER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.165V
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q
nQ
V
EE
V
CC
,
V
CCA
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
RMS P
HASE
J
ITTER
SCOPE
Qx
nQx
LVPECL
2V
-0.5V 0.125V
V
EE
V
CC
,
V
CCA
843081AGI-01
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REV. B JANUARY 23, 2006
7
Integrated
Circuit
Systems, Inc.
ICS843081I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL C
LOCK
M
ULTIPLIER
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843081I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
and V
CCA
should
b e i n d i v i d u a l l y c o n n e c t e d t o t h e p o w e r s u p p l y
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
pin. The 10
resistor can also be replaced by a ferrite bead.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V or 2.5V
.01
F
V
CC
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843081I-01 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2
below were determined using an 18pF parallel reso-
nant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
ICS843081I-01
C1
33p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN
843081AGI-01
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REV. B JANUARY 23, 2006
8
Integrated
Circuit
Systems, Inc.
ICS843081I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL C
LOCK
M
ULTIPLIER
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
to drive 50
transmission lines. Matched impedance tech-
niques should be used to maximize operating frequency and
minimize signal distortion.
Figures 3A and 3B
show two dif-
ferent layouts which are recommended only as guidelines.
Other suitable clock layouts may exist and it would be rec-
ommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component
process variations.
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
843081AGI-01
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REV. B JANUARY 23, 2006
9
Integrated
Circuit
Systems, Inc.
ICS843081I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL C
LOCK
M
ULTIPLIER
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 4A
and
Figure 4B
show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very close to
ground level. The R3 in Figure 4B can be eliminated and the
termination is shown in
Figure 4C.
F
IGURE
4C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
F
IGURE
4B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
F
IGURE
4A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
Zo = 50 Ohm
R1
250
+
-
2.5V
2,5V LVPECL
Driv er
R4
62.5
R3
250
Zo = 50 Ohm
2.5V
VCC=2.5V
R1
50
R3
18
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
VCC=2.5V
2.5V
R2
50
2,5V LVPECL
Driv er
VCC=2.5V
R1
50
R2
50
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
+
-
843081AGI-01
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REV. B JANUARY 23, 2006
10
Integrated
Circuit
Systems, Inc.
ICS843081I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL C
LOCK
M
ULTIPLIER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843081I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843081I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_TYP
= 3.465V * 78mA = 270.27mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power
_MAX
(3.465V, with all outputs switching) = 270.27mW + 30mW = 300.27mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.300W * 90.5C/W = 112C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
ABLE
6. T
HERMAL
R
ESISTANCE
JA
FOR
8-
PIN
TSSOP, F
ORCED
C
ONVECTION
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
843081AGI-01
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REV. B JANUARY 23, 2006
11
Integrated
Circuit
Systems, Inc.
ICS843081I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL C
LOCK
M
ULTIPLIER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
5. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
843081AGI-01
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REV. B JANUARY 23, 2006
12
Integrated
Circuit
Systems, Inc.
ICS843081I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL C
LOCK
M
ULTIPLIER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843081I-01 is: 1697
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
843081AGI-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 23, 2006
13
Integrated
Circuit
Systems, Inc.
ICS843081I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL C
LOCK
M
ULTIPLIER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
8 L
EAD
TSSOP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
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Y
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843081AGI-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 23, 2006
14
Integrated
Circuit
Systems, Inc.
ICS843081I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL C
LOCK
M
ULTIPLIER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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843081AGI-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 23, 2006
15
Integrated
Circuit
Systems, Inc.
ICS843081I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V, 2.5V LVPECL C
LOCK
M
ULTIPLIER
T
E
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