Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Functional Description
- Parallel & Serial Load Operations Diagram
- Pin Descriptions
- Pin Characteristics
- Parallel & Serial Mode Function Table
- Programmable VCO Frequency Function Table
- Programmable Output Divider Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Input Characteristics
- Crystal Characteristics
- AC Characteristics
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Recommendations for Unused Input & Output Pins
- Termination for LVPECL Outputs
- Layout Guideline
- Schematic of Recommended Layout
- Power & Grounding
- Clock Traces & Termination
- Crystal
- PCB Board Layout
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
8430BYI-71
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 17, 2006
1
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
I
NTERFACE
/
LVCMOS-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS8430BI-71 is a general purpose, dual out-
put Crystal/LVCMOS-to-3.3V Differential LVPECL
High Frequency Synthesizer and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The ICS8430BI-71 has a se-
lectable crystal oscillator interface or LVCMOS TEST_CLK.
The VCO operates at a frequency range of 250MHz to
700MHz. With the output configured to divide the VCO
frequency by 2, output frequency steps as small as 2MHz
can be achieved using a 16MHz crystal or test clock. Output
frequencies up to 700MHz can be programmed using the
serial or parallel interfaces to the configuration logic. The low
jitter and frequency range of the ICS8430BI-71 make it an
ideal clock generator for most clock tree applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Dual differential 3.3V LVPECL outputs
Selectable crystal oscillator interface
or LVCMOS TEST_CLK
Output frequency up to 700MHz
Crystal input frequency range: 12MHz to 27MHz
VCO range: 250MHz to 700MHz
Parallel or serial interface for programming counter
and output dividers
RMS period jitter: 9ps (maximum)
Cycle-to-cycle jitter: 25ps (maximum)
3.3V supply voltage
-40C to 85C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL_OUT
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N 0
N 1
N 2
V
EE
V
EE
nFOUT0
FOUT0
V
CCO
nFOUT1
FOUT1
V
CC
TEST
XT
AL_IN
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8430BI-71
HiPerClockSTM
ICS
OSC
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N2
VCO
PLL
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
N
CONFIGURATION
INTERFACE
LOGIC
M
0
1
0
1
16
PHASE DETECTOR
MR
2
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8430BYI-71
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 17, 2006
2
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
I
NTERFACE
/
LVCMOS-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
specific default state that will automatically occur during
power-up. The TEST output is LOW when operating in the
parallel input mode. The relationship between the VCO fre-
quency, the crystal frequency and the M divider is defined as
follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
16MHz reference are defined as 125
M 350. The frequency
out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-
to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data
at the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS8430BI-71 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A parallel-resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector. With a 16MHz crys-
tal, this provides a 1MHz reference frequency. The VCO of
the PLL operates over a range of 250MHz to 700MHz. The
output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by adjust-
ing the VCO control voltage. Note that for some values of M
(either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
each of the LVPECL output buffers. The divider provides a
50% output duty cycle.
The programmable features of the ICS8430BI-71 support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial.
Fig-
ure 1
shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on inputs
M0 through M8 and N0 through N2 is passed directly to the M
divider and N output divider. On the LOW-to-HIGH transition
of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and N bits can
be hardwired to set the M divider and N output divider to a
F
UNCTIONAL
D
ESCRIPTION
N
fout = fVCO =
16
2M
fxtal x
N
16
fVCO =
fxtal x 2M
T1
T0
TEST Output
0
0
LOW
0
1
S_Data clocked into register
1
0
Output of M divider
1
1
CMOS Fout
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
t
S
t
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t
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t
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t
S
M, N
T1
T0
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N2
nP_LOAD
S_LOAD
8430BYI-71
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 17, 2006
3
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
I
NTERFACE
/
LVCMOS-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
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8430BYI-71
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 17, 2006
4
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
I
NTERFACE
/
LVCMOS-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
(NOTE 1)
T
ABLE
3A. P
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8430BYI-71
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 17, 2006
5
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
I
NTERFACE
/
LVCMOS-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= -40C
TO
85C
l
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5
1
A
m
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
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T
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m
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M
s
t
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n
U
V
H
O
1
E
T
O
N
;
e
g
a
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l
o
V
h
g
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H
t
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p
t
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V
C
C
4
.
1
-
V
C
C
9
.
0
-
V
V
L
O
1
E
T
O
N
;
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g
a
t
l
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w
o
L
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u
p
t
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O
V
C
C
0
.
2
-
V
C
C
7
.
1
-
V
V
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