Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Function Description
- Frequency Margin Function Table
- Serial Load Operations
- Pin Descriptions
- Pin Characteristics
- OE Control Input Function Table
- SEL Control Input Function Table
- Mode Control Input Function Table
- Serial Mode Function Table
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- Power Supply 3.3V/2.5V DC Characteristics
- Power Supply 2.5V DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Crystal Characteristics
- Input Frequency Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- 2.5V AC Characteristics
- Typical Phase Noise Plot
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Recommendations for Unused Input and Output Pins
- Termination for 3.3V LVPECL Output
- Termination for 2.5V LVPECL Output
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
1
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS843101I-100 is a low phase-noise
frequency margining synthesizer with fre-
quency margining capability and is a member of
the HiPerClockSTM family of high performance
clock solutions from ICS. In the default mode,
the device nominally generates a 100MHz LVPECL output
clock signal from a 24MHz crystal input. There is also a
frequency margining mode available where the device can
be programmed, using the serial interface, to vary the
output frequency up or down from nominal in 2% steps.
The ICS843101I-100 is provided in a 16-pin TSSOP.
F
EATURES
100MHz nominal LVPECL output
Selectable crystal oscillator interface designed for 24MHz,
18pF parallel resonant crystal or LVCMOS/LVTTL
single-ended input
Output frequency can be varied in 2% steps from
nominal
VCO range: 540MHz - 680MHz
RMS phase jitter @ 100MHz, using a 24MHz crystal
(1.875MHz - 20MHz): 0.55ps (typical)
Output supply modes
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40C to 85C ambient operating temperature
Available in both standard and lead-free RoHS-complaint
packages
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
V
EE
S_LOAD
S_DATA
S_CLOCK
SEL
O E
V
CCA
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MODE
V
CCO
Q
nQ
V
EE
CLK
XTAL_OUT
XTAL_IN
ICS843101I-100
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
B
LOCK
D
IAGRAM
1
1
0
Phase
Detector
VCO
540 - 680MHz
M
OSC
N
P
Serial Control
Q
nQ
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
O E
CLK
SEL
S_CLOCK
S_DATA
S_LOAD
MODE
XTAL_IN
XTAL_OUT
Pulldown
24MHz
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
2
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
F
UNCTIONAL
D
ESCRIPTION
The ICS843101I-100 features a fully integrated PLL and
therefore requires no external components for setting the
loop bandwidth. A 24MHz fundamental crystal is used as
the input to the on chip oscillator. The output of the oscilla-
tor is fed into the pre-divider. In frequency margining mode,
the 24MHz crystal frequency is divided by 2 and a 12MHz
reference frequency is applied to the phase detector. The
VCO of the PLL operates over a range of 540MHz to
680MHz. The output of the M divider is also applied to the
phase detector.
The default mode for the ICS843101I-100 is 100MHz output
frequency using a 24MHz crystal. The output frequency
can be changed by placing the device into the margining
mode using the mode pin and using the serial interface to
program the M feedback divider. Frequency margining
mode operation occurs when the MODE input is HIGH. The
phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M
(either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by an output divider prior to
being sent to the LVPECL output buffer. The divider provides
a 50% output duty cycle. The relationship between the crys-
tal input frequency, the M divider, the VCO frequency and
the output frequency is provided in Table 1. When changing
back from frequency margining mode to nominal mode, the
device will return to the default nominal configuration that
will provide 100MHz output frequency.
Serial operation occurs when S_LOAD is HIGH. Serial data
can be loaded in either the default mode or the frequency
margining mode. The 6-bit shift register is loaded by samp-
ling the S_DATA bits with the rising edge of S_CLOCK.
After shifting in the 6-bit M divider value, S_LOAD is
transitioned from HIGH to LOW which latches the contents
of the shift-register into the M divider control register.
When S_LOAD is LOW, any transitions of S_CLOCK or
S_DATA are ignored.
T
ABLE
1. F
REQUENCY
M
ARGIN
F
UNCTION
T
ABLE
F
IGURE
1. S
ERIAL
L
OAD
O
PERATIONS
Time
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ERIAL
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843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
3
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
T
ABLE
2. P
IN
D
ESCRIPTIONS
T
ABLE
3. P
IN
C
HARACTERISTICS
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843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
4
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
T
ABLE
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F
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=
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F
=
843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
5
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
T
ABLE
5A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= -40C
TO
85C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
89C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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S
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DC C
HARACTERISTICS
,
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= V
CCA
= 3.3V5%,V
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= 2.5V5%, T
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TO
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DC C
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,
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= V
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= V
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= 2.5V5%, T
A
= -40C
TO
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A
m
843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
6
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
T
ABLE
6. C
RYSTAL
C
HARACTERISTICS
T
ABLE
5D. LVCMOS / LVTTL DC C
HARACTERISTICS
,
T
A
= -40C
TO
85C
T
ABLE
5E. LVPECL DC C
HARACTERISTICS
,
T
A
= -40C
TO
85C
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843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
7
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
T
ABLE
8A. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
8B. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%,V
CCO
= 2.5V5%, T
A
= -40C
TO
85C
T
ABLE
8C. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 2.5V5%, T
A
= -40C
TO
85C
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T
O
N
843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
8
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
O
FFSET
F
REQUENCY
(H
Z
)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
T
YPICAL
P
HASE
N
OISE
AT
100MH
Z
(3.3V)
100MHz
RMS Phase Noise Jitter
1.875MHz to 20MHz = 0.55ps (typical)
10 Gigabit Ethernet Filter
Raw Phase Noise Data
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
dBc
Hz
N
OISE
P
OWER
843101AGI-100
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REV. A OCTOBER 20, 2005
9
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.165V
RMS P
HASE
J
ITTER
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
V
CC
,
V
CCA
, V
CCO
V
EE
nQ
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
O
UTPUT
R
ISE
/F
ALL
T
IME
SCOPE
Qx
nQx
LVPECL
2.8V0.04V
-0.5V 0.125V
V
CC
,
V
CCA
V
EE
V
CCO
2V
SCOPE
Qx
nQx
LVPECL
2V
-0.5V 0.125V
V
CC
,
V
CCA
, V
CCO
V
EE
843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
10
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843101I-100 pro-
vides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. V
CC
, V
CCA
, and
V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
. The 10
resis-
tor can also be replaced by a ferrite bead.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V or 2.5V
.01
F
V
CC
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843101I-100 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 3
below were determined using a 24MHz, 18pF par-
Figure 3. C
RYSTAL
I
NPU
t I
NTERFACE
allel resonant crystal and were chosen to minimize the
ppm error.
C1
27p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
843101AGI-100
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REV. A OCTOBER 20, 2005
11
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
F
IGURE
4B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
4A. LVPECL O
UTPUT
T
ERMINATION
outputs are designed to drive 50
transmission lines.
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion.
Figures 4A and 4B
show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1k
resistor can be
tied from XTAL_IN to ground.
CLK I
NPUT
:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1k
resistor can be tied from the CLK input to ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
12
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 5A
and
Figure 5B
show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to
terminating 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is
very close to ground level. The R3 in Figure 4B can be
eliminated and the termination is shown in
Figure 4C.
F
IGURE
5C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
F
IGURE
5B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
F
IGURE
5A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
Zo = 50 Ohm
R1
250
+
-
2.5V
2,5V LVPECL
Driv er
R4
62.5
R3
250
Zo = 50 Ohm
2.5V
VCC=2.5V
R1
50
R3
18
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
VCC=2.5V
2.5V
R2
50
2,5V LVPECL
Driv er
VCC=2.5V
R1
50
R2
50
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
+
-
843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
13
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843101I-100.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843101I-100 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 92mA = 318.78mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power
_MAX
(3.63V, with all outputs switching) = 318.78mW + 30mW = 348.78mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.349W *81.8C/W = 113.5C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
137.1C/W
118.2C/W
106.8C/W
Multi-Layer PCB, JEDEC Standard Test Boards
89.0C/W
81.8C/W
78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
7. T
HERMAL
R
ESISTANCE
JA
FOR
16-
PIN
TSSOP, F
ORCED
C
ONVECTION
843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
14
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
5. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
15
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843101I-100 is: 4093
T
ABLE
9.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
16 L
EAD
TSSOP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
137.1C/W
118.2C/W
106.8C/W
Multi-Layer PCB, JEDEC Standard Test Boards
89.0C/W
81.8C/W
78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
16
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
20 L
EAD
TSSOP
T
ABLE
10. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
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843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
17
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
T
ABLE
11. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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