Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Functional Description
- Parallel & Serial Load Operations Diagram
- N Output Divider Function Table
- SSC Function Table
- Pin Descriptions
- Pin Characteristics
- Parallel & Serial Mode Function Table
- Programmable VCO Frequency Function Table
- Programmable Output Divider Function Table
- Absolute Maximum Ratings
- 3.3V Power Supply DC Characteristics
- 3.3V/2.5V Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Input Frequency Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Recommendations for Unused Input and Output Pins
- Crystal Input Interface
- Termination for 3.3V LVPECL Outputs
- Termination for 2.5V LVPECL Outputs
- Layout Guideline
- Schematic Layout
- Power & Grounding
- Clock Traces & Termination
- Crystal
- PCB Board Layout
- Spread Spectrum
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
1
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS84314-02 is a general purpose quad
output frequency synthesizer and a member of
the HiPerClockSTM family of High Performance
Clock Solutions from ICS. When the device uses
parallel loading, the M bits are programmable and
the output divider is hard-wired for divide by 2 thus providing
a frequency range of 125MHz to 350MHz. In serial program-
ming mode, the M bits are programmable and the output
divider can be set for either divide by 1, 2, 4 or divide by 8,
providing a frequency range of 31.25MHz to 700MHz.
Additionally, the device supports spread spectrum clocking
(SSC) for minimizing Electromagnetic Interference (EMI). The
low cycle-cycle jitter and broad frequency range of the
ICS84314-02 make it an ideal clock generator for a variety of
demanding applications which require high performance.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Fully integrated PLL
Four differential 3.3V or 2.5V LVPECL outputs
Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK input
Output frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
Supports Spread Spectrum Clocking (SSC)
Parallel interface for programming counter
and output dividers during power-up
Serial 3 wire interface
Cycle-to-cycle jitter: 20ps (typical)
Output skew: TBD
Output duty cycle: TBD
Full 3.3V or mixed 3.3V core, 2.5V output operating supply
0C to 85C ambient operating temperature
Available in both standard and lead-free RoHS-complaint
packages
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
V
CCO
M4
M5
M6
M7
M8
V
EE
V
CC
V
CCO
XT
AL_IN
XT
AL_OUT
nP_LOAD
VCO_SEL
M0
M1
M2
M3
OSC
VCO
PLL
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Output Divider N
1 Serial Mode
2 Parallel/Serial Mode
(Power-up Default)
4 Serial Mode
8 Serial Mode
CONFIGURATION
INTERFACE
LOGIC
M
0
1
0
1
16
PHASE DETECTOR
ICS84314-02
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
Top View
HiPerClockSTM
ICS
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
MR
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
2
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
2
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 is passed directly to the M divider. On the LOW-to-HIGH tran-
sition of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or until
a serial event occurs. As a result, the M bits can be hardwired to
set the M divider to a specific default state that will automatically
occur during power-up. In parallel mode, the N output divider is
set to 2. In serial mode, the N output divider can be set for either
1, 2, 4 or 8. The relationship between the VCO frequency,
the crystal frequency and the M divider is defined as follows:
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 16MHz refer-
ence are defined as 125
M 350. The frequency out
is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA bits
with the rising edge of S_CLOCK. The contents of the shift regis-
ter are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N out-
put divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is
passed directly to the M divider and N output divider on each
rising edge of S_CLOCK.
NOTE: The functional description that follows describes
operation using a 16MHz crystal. Valid PLL loop divider
values for different crystal or input frequencies are defined
in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS84314-02 features a fully integrated PLL and there-
fore requires no external components for setting the loop
bandwidth. A parallel-resonant, fundamental crystal is used
as the input to the on-chip oscillator. The output of the os-
cillator is divided by 16 prior to the phase detector. With a
16MHz crystal, this provides a 1MHz reference frequency.
The VCO of the PLL operates over a range of 250MHz to
700MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by ad-
justing the VCO control voltage. Note that for some values
of M (either too high or too low), the PLL will not achieve
lock. The output of the VCO is scaled by a divider prior to
being sent to each of the LVPECL output buffers. The divider
provides a 50% output duty cycle.
The programmable features of the ICS84314-02 support
two input modes to program the M divider. The two input
operational modes are parallel and serial.
Figure 1
shows
the timing diagram for each mode. In parallel mode, the
F
UNCTIONAL
D
ESCRIPTION
16
fVCO =
fxtal x 2M
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8
nP_LOAD
S_LOAD
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
t
S
t
H
t
S
t
H
t
S
M, N
*NULL *NULL SSC0 **N1
**N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
*NOTE: The NULL timing slot must be observed.
**NOTE: "N" can only be controlled through serial loading.
fout = fVCO
=
16
2M
fxtal x
N
1
x
N
1
x
e
u
l
a
V
c
i
g
o
L
1
N
e
u
l
a
V
c
i
g
o
L
0
N
e
d
i
v
i
D
t
u
p
t
u
O
N
0
0
1
0
1
)
t
l
u
a
f
e
D
p
u
-
r
e
w
o
P
(
2
1
0
4
1
1
8
T
ABLE
1A. N O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
(S
ERIAL
L
OAD
)
0
C
S
S
e
t
a
t
S
C
S
S
0
)
t
l
u
a
f
e
D
p
u
-
r
e
w
o
P
(
f
f
O
1
D
B
T
T
ABLE
1B. SSC F
UNCTION
T
ABLE
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
3
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
2. P
IN
D
ESCRIPTIONS
r
e
b
m
u
N
e
m
a
N
e
p
y
T
n
o
i
t
p
i
r
c
s
e
D
5
,
2
,
1
1
3
,
0
3
,
9
2
,
8
M
,
5
M
,
4
M
2
M
,
1
M
,
0
M
t
u
p
n
I
n
w
o
d
ll
u
P
n
o
i
t
i
s
n
a
r
t
H
G
I
H
-
o
t
-
W
O
L
n
o
d
e
h
c
t
a
l
a
t
a
D
.
s
t
u
p
n
i
r
e
d
i
v
i
d
M
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
t
u
p
n
i
D
A
O
L
_
P
n
f
o
2
3
,
4
,
3
3
M
,
7
M
,
6
M
t
u
p
n
I
p
u
ll
u
P
6
V
E
E
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
e
v
i
t
a
g
e
N
7
V
C
C
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
r
e
w
o
p
e
r
o
C
7
1
,
8
V
O
C
C
r
e
w
o
P
.
s
n
i
p
y
l
p
p
u
s
t
u
p
t
u
O
0
1
,
9
0
Q
n
,
0
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
C
E
P
V
L
.
r
e
z
i
s
e
h
t
n
y
s
e
h
t
r
o
f
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
2
1
,
1
1
1
Q
n
,
1
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
C
E
P
V
L
.
r
e
z
i
s
e
h
t
n
y
s
e
h
t
r
o
f
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
4
1
,
3
1
2
Q
n
,
2
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
C
E
P
V
L
.
r
e
z
i
s
e
h
t
n
y
s
e
h
t
r
o
f
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
6
1
,
5
1
3
Q
n
,
3
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
C
E
P
V
L
.
r
e
z
i
s
e
h
t
n
y
s
e
h
t
r
o
f
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
8
1
R
M
t
u
p
n
I
n
w
o
d
ll
u
P
s
r
e
d
i
v
i
d
l
a
n
r
e
t
n
i
e
h
t
,
H
G
I
H
c
i
g
o
l
n
e
h
W
.
t
e
s
e
R
r
e
t
s
a
M
h
g
i
H
e
v
i
t
c
A
d
e
t
r
e
v
n
i
e
h
t
d
n
a
w
o
l
o
g
o
t
x
Q
s
t
u
p
t
u
o
e
u
r
t
e
h
t
g
n
i
s
u
a
c
t
e
s
e
r
e
r
a
d
n
a
s
r
e
d
i
v
i
d
l
a
n
r
e
t
n
i
e
h
t
,
W
O
L
c
i
g
o
l
n
e
h
W
.
h
g
i
h
o
g
o
t
x
Q
n
s
t
u
p
t
u
o
d
e
d
a
o
l
t
c
e
f
f
a
t
o
n
s
e
o
d
R
M
f
o
n
o
i
t
r
e
s
s
A
.
d
e
l
b
a
n
e
e
r
a
s
t
u
p
t
u
o
e
h
t
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
s
e
u
l
a
v
M
9
1
K
C
O
L
C
_
S
t
u
p
n
I
n
w
o
d
ll
u
P
r
e
t
s
i
g
e
r
t
f
i
h
s
e
h
t
o
t
n
i
t
u
p
n
i
A
T
A
D
_
S
t
a
t
n
e
s
e
r
p
a
t
a
d
l
a
i
r
e
s
n
i
s
k
c
o
l
C
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
K
C
O
L
C
_
S
f
o
e
g
d
e
g
n
i
s
i
r
e
h
t
n
o
0
2
A
T
A
D
_
S
t
u
p
n
I
n
w
o
d
ll
u
P
e
g
d
e
g
n
i
s
i
r
e
h
t
n
o
d
e
l
p
m
a
s
a
t
a
D
.
t
u
p
n
i
l
a
i
r
e
s
r
e
t
s
i
g
e
r
t
f
i
h
S
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
K
C
O
L
C
_
S
f
o
1
2
D
A
O
L
_
S
t
u
p
n
I
n
w
o
d
ll
u
P
.
s
r
e
d
i
v
i
d
e
h
t
o
t
n
i
r
e
t
s
i
g
e
r
t
f
i
h
s
m
o
r
f
a
t
a
d
f
o
n
o
i
t
i
s
n
a
r
t
s
l
o
r
t
n
o
C
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
2
2
V
A
C
C
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
g
o
l
a
n
A
3
2
L
E
S
_
L
A
T
X
t
u
p
n
I
p
u
ll
u
P
L
L
P
e
h
t
s
a
k
c
o
l
c
t
s
e
t
r
o
r
o
t
a
ll
i
c
s
o
l
a
t
s
y
r
c
e
h
t
n
e
e
w
t
e
b
s
t
c
e
l
e
S
s
t
c
e
l
e
S
.
H
G
I
H
n
e
h
w
s
t
u
p
n
i
L
A
T
X
s
t
c
e
l
e
S
.
e
c
r
u
o
s
e
c
n
e
r
e
f
e
r
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
W
O
L
n
e
h
w
K
L
C
_
T
S
E
T
4
2
K
L
C
_
T
S
E
T
t
u
p
n
I
n
w
o
d
ll
u
P
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
t
u
p
n
i
k
c
o
l
c
t
s
e
T
6
2
,
5
2
,
N
I
_
L
A
T
X
T
U
O
_
L
A
T
X
t
u
p
n
I
.
t
u
p
n
i
e
h
t
s
i
N
I
_
L
A
T
X
.
e
c
a
f
r
e
t
n
i
r
o
t
a
ll
i
c
s
o
l
a
t
s
y
r
C
.
t
u
p
t
u
o
e
h
t
s
i
T
U
O
_
L
A
T
X
7
2
D
A
O
L
_
P
n
t
u
p
n
I
n
w
o
d
ll
u
P
0
M
:
8
M
t
a
t
n
e
s
e
r
p
a
t
a
d
n
e
h
w
s
e
n
i
m
r
e
t
e
D
.
t
u
p
n
i
d
a
o
l
l
e
ll
a
r
a
P
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
r
e
d
i
v
i
d
M
e
h
t
o
t
n
i
d
e
d
a
o
l
s
i
8
2
L
E
S
_
O
C
V
t
u
p
n
I
p
u
ll
u
P
.
e
d
o
m
s
s
a
p
y
b
r
o
L
L
P
n
i
s
i
r
e
z
i
s
e
h
t
n
y
s
r
e
h
t
e
h
w
s
e
n
i
m
r
e
t
e
D
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
:
E
T
O
N
p
u
ll
u
P
d
n
a
n
w
o
d
ll
u
P
.
s
e
u
l
a
v
l
a
c
i
p
y
t
r
o
f
,
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
n
i
P
,
2
e
l
b
a
T
e
e
S
.
s
r
o
t
s
i
s
e
r
t
u
p
n
i
l
a
n
r
e
t
n
i
o
t
r
e
f
e
r
T
ABLE
3. P
IN
C
HARACTERISTICS
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
C
N
I
e
c
n
a
t
i
c
a
p
a
C
t
u
p
n
I
4
F
p
R
P
U
L
L
U
P
r
o
t
s
i
s
e
R
p
u
ll
u
P
t
u
p
n
I
1
5
k
R
N
W
O
D
L
L
U
P
r
o
t
s
i
s
e
R
n
w
o
d
ll
u
P
t
u
p
n
I
1
5
k
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
4
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
4B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
(NOTE 1)
T
ABLE
4A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
y
c
n
e
u
q
e
r
F
O
C
V
)
z
H
M
(
e
d
i
v
i
D
M
6
5
2
8
2
1
4
6
2
3
6
1
8
4
2
1
8
M
7
M
6
M
5
M
4
M
3
M
2
M
1
M
0
M
0
5
2
5
2
1
0
0
1
1
1
1
1
0
1
2
5
2
6
2
1
0
0
1
1
1
1
1
1
0
4
5
2
7
2
1
0
0
1
1
1
1
1
1
1
6
5
2
8
2
1
0
1
0
0
0
0
0
0
0
6
9
6
8
4
3
1
0
1
0
1
1
1
0
0
8
9
6
9
4
3
1
0
1
0
1
1
1
0
1
0
0
7
0
5
3
1
0
1
0
1
1
1
1
0
t
u
p
n
i
K
L
C
_
T
S
E
T
r
o
l
a
t
s
y
r
c
o
t
d
n
o
p
s
e
r
r
o
c
s
e
i
c
n
e
u
q
e
r
f
g
n
i
t
l
u
s
e
r
e
h
t
d
n
a
s
e
u
l
a
v
e
d
i
v
i
d
M
e
s
e
h
T
:
1
E
T
O
N
.
z
H
M
6
1
f
o
y
c
n
e
u
q
e
r
f
s
t
u
p
n
I
s
n
o
i
t
i
d
n
o
C
R
M
D
A
O
L
_
P
n
M
D
A
O
L
_
S
K
C
O
L
C
_
S
A
T
A
D
_
S
H
X
X
X
X
X
.
W
O
L
s
t
u
p
t
u
o
s
e
c
r
o
F
.
t
e
s
e
R
L
L
a
t
a
D
X
X
X
.
r
e
d
i
v
i
d
M
e
h
t
o
t
y
l
t
c
e
r
i
d
d
e
s
s
a
p
s
t
u
p
n
i
M
n
o
a
t
a
D
L
a
t
a
D
L
X
X
d
e
d
a
o
l
s
n
i
a
m
e
r
d
n
a
s
r
e
t
s
i
g
e
r
t
u
p
n
i
o
t
n
i
d
e
h
c
t
a
l
s
i
a
t
a
D
.
s
r
u
c
c
o
t
n
e
v
e
l
a
i
r
e
s
a
li
t
n
u
r
o
n
o
i
t
i
s
n
a
r
t
W
O
L
t
x
e
n
li
t
n
u
L
H
X
L
a
t
a
D
n
o
a
t
a
d
h
t
i
w
d
e
d
a
o
l
s
i
r
e
t
s
i
g
e
r
t
f
i
h
S
.
e
d
o
m
t
u
p
n
i
l
a
i
r
e
S
.
K
C
O
L
C
_
S
f
o
e
g
d
e
g
n
i
s
i
r
h
c
a
e
n
o
A
T
A
D
_
S
L
H
X
L
a
t
a
D
e
h
t
o
t
d
e
s
s
a
p
e
r
a
r
e
t
s
i
g
e
r
t
f
i
h
s
e
h
t
f
o
s
t
n
e
t
n
o
C
.
r
e
d
i
v
i
d
t
u
p
t
u
o
N
d
n
a
r
e
d
i
v
i
d
M
L
H
X
L
a
t
a
D
.
d
e
h
c
t
a
l
e
r
a
s
e
u
l
a
v
r
e
d
i
v
i
d
t
u
p
t
u
o
N
d
n
a
r
e
d
i
v
i
d
M
L
H
X
L
X
X
.
s
r
e
t
s
i
g
e
r
t
f
i
h
s
t
c
e
f
f
a
t
o
n
o
d
t
u
p
n
i
l
a
i
r
e
s
r
o
l
e
ll
a
r
a
P
L
H
X
H
a
t
a
D
.
d
e
k
c
o
l
c
s
i
t
i
s
a
r
e
d
i
v
i
d
M
o
t
y
l
t
c
e
r
i
d
d
e
s
s
a
p
A
T
A
D
_
S
W
O
L
=
L
:
E
T
O
N
H
G
I
H
=
H
e
r
a
c
t
'
n
o
D
=
X
n
o
i
t
i
s
n
a
r
t
e
g
d
e
g
n
i
s
i
R
=
n
o
i
t
i
s
n
a
r
t
e
g
d
e
g
n
il
l
a
F
=
t
u
p
n
I
)
z
H
M
(
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
c
i
g
o
L
1
N
c
i
g
o
L
0
N
e
d
i
v
i
D
N
3
Q
n
:
0
Q
n
,
3
Q
:
0
Q
m
u
m
i
n
i
M
m
u
m
i
x
a
M
0
0
1
0
5
2
0
0
7
0
1
2
5
2
1
0
5
3
1
0
4
5
.
2
6
5
7
1
1
1
8
5
2
.
1
3
5
.
7
8
T
ABLE
4C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
(S
ERIAL
P
ROGRAMMING
M
ODE
O
NLY
)
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
5
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
5A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
85C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
C
C
e
g
a
t
l
o
V
y
l
p
p
u
S
e
r
o
C
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
A
C
C
e
g
a
t
l
o
V
y
l
p
p
u
S
g
o
l
a
n
A
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
O
C
C
e
g
a
t
l
o
V
y
l
p
p
u
S
t
u
p
t
u
O
5
7
3
.
2
5
.
2
5
2
6
.
2
V
I
E
E
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
D
B
T
A
m
I
A
C
C
t
n
e
r
r
u
C
y
l
p
p
u
S
g
o
l
a
n
A
D
B
T
A
m
T
ABLE
5B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO
= 3.3V5%
OR
2.5V5%, T
A
= 0C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
C
C
e
g
a
t
l
o
V
y
l
p
p
u
S
e
r
o
C
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
A
C
C
e
g
a
t
l
o
V
y
l
p
p
u
S
g
o
l
a
n
A
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
O
C
C
e
g
a
t
l
o
V
y
l
p
p
u
S
t
u
p
t
u
O
5
3
1
.
3
3
.
3
5
6
4
.
3
V
I
E
E
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
D
B
T
A
m
I
A
C
C
t
n
e
r
r
u
C
y
l
p
p
u
S
g
o
l
a
n
A
D
B
T
A
m
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
6
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
6. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO
= 3.3V5%
OR
2.5V5%, T
A
= 0C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
N
I
y
c
n
e
u
q
e
r
F
t
u
p
n
I
1
E
T
O
N
;
K
L
C
_
T
S
E
T
0
1
0
4
z
H
M
;
T
U
O
_
L
A
T
X
,
N
I
_
L
A
T
X
1
E
T
O
N
2
1
0
4
z
H
M
K
C
O
L
C
_
S
0
5
z
H
M
e
h
t
n
i
h
t
i
w
e
t
a
r
e
p
o
o
t
O
C
V
e
h
t
r
o
f
t
e
s
e
b
t
s
u
m
e
u
l
a
v
M
e
h
t
,
e
g
n
a
r
y
c
n
e
u
q
e
r
f
e
c
n
e
r
e
f
e
r
d
n
a
l
a
t
s
y
r
c
t
u
p
n
i
e
h
t
r
o
F
:
1
E
T
O
N
7
6
1
e
r
a
M
f
o
s
e
u
l
a
v
d
il
a
v
,
z
H
M
2
1
f
o
y
c
n
e
u
q
e
r
f
t
u
p
n
i
m
u
m
i
n
i
m
e
h
t
g
n
i
s
U
.
e
g
n
a
r
z
H
M
0
0
7
o
t
z
H
M
0
5
2
M
.
6
6
4
0
5
e
r
a
M
f
o
s
e
u
l
a
v
d
il
a
v
,
z
H
M
0
4
f
o
y
c
n
e
u
q
e
r
f
m
u
m
i
x
a
m
e
h
t
g
n
i
s
U
M
.
0
4
1
T
ABLE
7. C
RYSTAL
C
HARACTERISTICS
T
ABLE
5D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO
= 3.3V5%
OR
2.5V5%, T
A
= 0C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
O
1
E
T
O
N
;
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
V
O
C
C
4
.
1
-
V
O
C
C
9
.
0
-
V
V
L
O
1
E
T
O
N
;
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
V
O
C
C
0
.
2
-
V
O
C
C
7
.
1
-
V
V
G
N
I
W
S
g
n
i
w
S
e
g
a
t
l
o
V
t
u
p
t
u
O
k
a
e
P
-
o
t
-
k
a
e
P
6
.
0
0
.
1
V
0
5
h
t
i
w
d
e
t
a
n
i
m
r
e
t
s
t
u
p
t
u
O
:
1
E
T
O
N
V
o
t
O
C
C
,
n
o
i
t
c
e
s
"
n
o
i
t
a
m
r
o
f
n
I
t
n
e
m
e
r
u
s
a
e
M
r
e
t
e
m
a
r
a
P
"
e
e
S
.
V
2
-
.
s
m
a
r
g
a
i
d
"
t
i
u
c
r
i
C
t
s
e
T
d
a
o
L
t
u
p
t
u
O
"
T
ABLE
5C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO
= 3.3V5%
OR
2.5V5%, T
A
= 0C
TO
85C
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
n
o
i
t
a
ll
i
c
s
O
f
o
e
d
o
M
l
a
t
n
e
m
a
d
n
u
F
y
c
n
e
u
q
e
r
F
2
1
0
4
z
H
M
)
R
S
E
(
e
c
n
a
t
s
i
s
e
R
s
e
i
r
e
S
t
n
e
l
a
v
i
u
q
E
0
5
e
c
n
a
t
i
c
a
p
a
C
t
n
u
h
S
7
F
p
l
e
v
e
L
e
v
i
r
D
1
W
m
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
I
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
2
V
C
C
3
.
0
+
V
V
L
I
e
g
a
t
l
o
V
w
o
L
t
u
p
n
I
3
.
0
-
8
.
0
V
I
H
I
t
u
p
n
I
t
n
e
r
r
u
C
h
g
i
H
,
R
M
,
8
M
,
5
M
,
4
M
,
2
M
:
0
M
,
K
C
O
L
C
_
S
,
D
A
O
L
_
P
n
D
A
O
L
_
S
,
A
T
A
D
_
S
V
C
C
V
=
N
I
V
5
6
4
.
3
=
0
5
1
A
,
7
M
,
6
M
,
3
M
L
E
S
_
O
C
V
,
L
E
S
_
L
A
T
X
V
C
C
V
=
N
I
V
5
6
4
.
3
=
5
A
K
L
C
_
T
S
E
T
V
C
C
V
=
N
I
V
5
6
4
.
3
=
0
0
2
A
I
L
I
t
u
p
n
I
t
n
e
r
r
u
C
w
o
L
,
R
M
,
8
M
,
5
M
,
4
M
,
2
M
:
0
M
,
K
C
O
L
C
_
S
,
D
A
O
L
_
P
n
D
A
O
L
_
S
,
A
T
A
D
_
S
V
C
C
,
V
5
6
4
.
3
=
V
N
I
V
0
=
5
-
A
,
7
M
,
6
M
,
3
M
L
E
S
_
O
C
V
,
L
E
S
_
L
A
T
X
V
C
C
,
V
5
6
4
.
3
=
V
N
I
V
0
=
0
5
1
-
A
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
7
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
8A. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
85C
T
ABLE
8B. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO
= 2.5V5%, T
A
= 0C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
F
X
A
M
e
g
n
a
R
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
5
2
.
1
3
0
0
7
z
H
M
t
)
c
c
(
t
ij
3
,
1
E
T
O
N
;
r
e
t
t
i
J
e
l
c
y
C
-
o
t
-
e
l
c
y
C
0
2
s
p
t
)
r
e
p
(
t
ij
1
E
T
O
N
;
S
M
R
,
r
e
t
t
i
J
d
o
i
r
e
P
D
B
T
s
p
t
)
o
(
k
s
3
,
2
E
T
O
N
;
w
e
k
S
t
u
p
t
u
O
D
B
T
s
p
t
R
t
/
F
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
6
4
s
p
t
S
e
m
i
T
p
u
t
e
S
D
A
O
L
_
P
n
o
t
M
5
s
n
K
C
O
L
C
_
S
o
t
A
T
A
D
_
S
5
s
n
D
A
O
L
_
S
o
t
K
C
O
L
C
_
S
5
s
n
t
H
e
m
i
T
d
l
o
H
D
A
O
L
_
P
n
o
t
M
5
s
n
K
C
O
L
C
_
S
o
t
A
T
A
D
_
S
5
s
n
D
A
O
L
_
S
o
t
K
C
O
L
C
_
S
5
s
n
F
M
4
E
T
O
N
;
y
c
n
e
u
q
e
r
F
n
o
i
t
a
l
u
d
o
M
C
S
S
0
3
3
3
.
3
3
z
H
k
F
F
M
4
E
T
O
N
;
r
o
t
c
a
F
n
o
i
t
a
l
u
d
o
M
C
S
S
4
.
0
6
.
0
%
C
S
S
d
e
r
4
E
T
O
N
;
n
o
i
t
c
u
d
e
R
l
a
r
t
c
e
p
S
7
0
1
B
d
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
0
5
%
t
K
C
O
L
e
m
i
T
k
c
o
L
L
L
P
1
s
m
.
n
o
i
t
c
e
s
n
o
i
t
a
m
r
o
f
n
I
t
n
e
m
e
r
u
s
a
e
M
r
e
t
e
m
a
r
a
P
e
e
S
.
s
t
u
p
n
i
l
a
t
s
y
r
c
g
n
i
s
u
e
c
n
a
m
r
o
f
r
e
p
r
e
t
t
i
J
:
1
E
T
O
N
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
d
n
a
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
2
E
T
O
N
.
s
t
n
i
o
p
s
s
o
r
c
l
a
i
t
n
e
r
e
f
f
i
d
t
u
p
t
u
o
e
h
t
t
a
d
e
r
u
s
a
e
M
.
5
6
d
r
a
d
n
a
t
S
C
E
D
E
J
h
t
i
w
e
c
n
a
d
r
o
c
c
a
n
i
d
e
n
i
f
e
d
s
i
r
e
t
e
m
a
r
a
p
s
i
h
T
:
3
E
T
O
N
.
d
e
l
b
a
n
e
g
n
i
k
c
o
l
c
m
u
r
t
c
e
p
S
d
a
e
r
p
S
:
4
E
T
O
N
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
F
X
A
M
e
g
n
a
R
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
5
2
.
1
3
0
0
7
z
H
M
t
)
c
c
(
t
ij
3
,
1
E
T
O
N
;
r
e
t
t
i
J
e
l
c
y
C
-
o
t
-
e
l
c
y
C
0
2
s
p
t
)
r
e
p
(
t
ij
1
E
T
O
N
;
S
M
R
,
r
e
t
t
i
J
d
o
i
r
e
P
D
B
T
s
p
t
)
o
(
k
s
3
,
2
E
T
O
N
;
w
e
k
S
t
u
p
t
u
O
D
B
T
s
p
t
R
t
/
F
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
6
4
s
p
t
S
e
m
i
T
p
u
t
e
S
D
A
O
L
_
P
n
o
t
M
5
s
n
K
C
O
L
C
_
S
o
t
A
T
A
D
_
S
5
s
n
D
A
O
L
_
S
o
t
K
C
O
L
C
_
S
5
s
n
t
H
e
m
i
T
d
l
o
H
D
A
O
L
_
P
n
o
t
M
5
s
n
K
C
O
L
C
_
S
o
t
A
T
A
D
_
S
5
s
n
D
A
O
L
_
S
o
t
K
C
O
L
C
_
S
5
s
n
F
M
4
E
T
O
N
;
y
c
n
e
u
q
e
r
F
n
o
i
t
a
l
u
d
o
M
C
S
S
0
3
3
3
.
3
3
z
H
k
F
F
M
4
E
T
O
N
;
r
o
t
c
a
F
n
o
i
t
a
l
u
d
o
M
C
S
S
4
.
0
6
.
0
%
C
S
S
d
e
r
4
E
T
O
N
;
n
o
i
t
c
u
d
e
R
l
a
r
t
c
e
p
S
7
0
1
B
d
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
0
5
%
t
K
C
O
L
e
m
i
T
k
c
o
L
L
L
P
1
s
m
.
e
v
o
b
a
A
8
e
l
b
a
T
n
i
s
e
t
o
n
e
e
S
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
8
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
P
ERIOD
J
ITTER
C
YCLE
-
TO
-C
YCLE
J
ITTER
O
UTPUT
S
KEW
SCOPE
Qx
nQx
LVPECL
2V
O
UTPUT
R
ISE
/F
ALL
T
IME
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
contains 68.26% of all measurements
2
contains 95.4% of all measurements
3
contains 99.73% of all measurements
4
contains 99.99366% of all measurements
6
contains (100-1.973x10
-7
)% of all measurements
Histogram
-1.3V 0.165V
t
sk(o)
nQx
Qx
nQy
Qy
nQx
Qx
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q0:Q3
nQ0:nQ3
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2.8V0.04V
-0.5V 0.125V
V
CC
,
V
CCA
2V
V
CCO
V
CC
,
V
CCA
, V
CCO
V
EE
V
EE
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
9
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84314-02 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
resistor can be tied from XTAL_IN to ground.
TEST_CLK I
NPUT
:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the TEST_CLK to
ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
10
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
Figure 3. C
RYSTAL
I
NPU
t I
NTERFACE
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS84314-02 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 3
below were determined using a 25MHz, 18pF paral-
lel resonant crystal and were chosen to minimize the ppm
error. The optimum C1 and C2 values can be slightly adjusted
for different board layouts.
ICS84332
XTAL_IN
XTAL_OUT
X1
18pF Parallel Cry stal
C2
22p
C1
22p
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
4B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
4A. LVPECL O
UTPUT
T
ERMINATION
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 4A and 4B
show two different lay-
outs which are recommended only as guidelines. Other suit-
able clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process varia-
tions.
T
ERMINATION
FOR
3.3V LVPECL O
UTPUTS
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
11
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 5A
and
Figure 5B
show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to ter-
minating 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very
close to ground level. The R3 in Figure 5A can be eliminated
and the termination is shown in
Figure 5C.
F
IGURE
5C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driv er
F
IGURE
5B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driv er
Zo = 50 Ohm
+
-
2.5V
F
IGURE
5A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driv er
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
12
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
C5
0.1u
VCCO=3.3V
VCC
R2
50
X1
Set Logic
Input to
'1'
RU2
Not Install
C4
0.1u
Zo = 50 Ohm
VCC
C3
0.1u
R7
10
R5
50
Set Logic
Input to
'0'
VC
C
C7 (Option)
0.1u
To Logic
Input
pins
R3
50
RU1
1K
Logic Input Pin Examples
+
-
VCC
VCCA
U1
ICS84314_02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
M4
M5
M6
M7
M8
VEE
VCC
VCCO
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
VCCO
MR
S_CLOCK
S_DATA
S_LOAD
VCCA
XTAL_SEL
T_CLK
M3
M2
M1
M0
VC
O
_
S
EL
nP
_LO
A
D
X_
O
U
T
X_
I
N
C1
RD1
Not Install
C2
Zo = 50 Ohm
Zo = 50 Ohm
VCC
VCC=3.3V
VCCO
RD2
1K
Zo = 50 Ohm
C6 (Option)
0.1u
VCCO
C11
0.01u
C16
10u
R4
50
R1
50
R6
50
To Logic
Input
pins
+
-
The schematic of the ICS84314-02 layout example used in
this layout guideline is shown in
Figure 6A.
The ICS84314-02
recommended PCB board layout for this example is shown
in
Figure 6B.
This layout example is used as a general
L
AYOUT
G
UIDELINE
F
IGURE
6A. S
CHEMATIC
OF
3.3V/3.3V R
ECOMMENDED
L
AYOUT
guideline. The layout in the actual system will depend on the
selected component types, the density of the components,
the density of the traces, and the stack up of the P.C. board.
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
13
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C14 and C15 as close as
possible to the power pins. If space allows, placing the
decoupling capacitor at the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin generated by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the
power (ground) plane and the component power (ground) pins.
If V
CCA
shares the same power supply with V
CC
, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the V
CCA
as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
The component placements, locations and orientations should
be arranged to achieve the best clock signal quality. Poor clock
signal quality can degrade the system performance or cause
system failure. In the synchronous high-speed digital system,
the clock signal is less tolerable to poor signal quality than other
signals. Any ringing on the rising or falling edge or excessive
ring back can cause system failure. The trace shape and the
trace delay might be restricted by the available space on the
board and the component location. While routing the traces, the
clock signal traces should be routed first and should be locked
prior to routing other signal traces.
The traces with 50
transmission lines TL1 and TL2
at FOUT and nFOUT should have equal delay and
run adjacent to each other. Avoid sharp angles on the
clock trace. Sharp angle turns cause the characteris-
tic impedance to change on the transmission lines.
Keep the clock trace on the same layer. Whenever pos-
sible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
To prevent cross talk, avoid routing other signal traces
in parallel with the clock traces. If running parallel traces
is unavoidable, allow more space between the clock
trace and the other signal trace.
Make sure no other signal trace is routed between the
clock trace pair.
The matching termination resistors R1, R2, R3 and R4
should be located as close to the receiver input pins as
possible. Other termination schemes can also be used but
are not shown in this example.
C
RYSTAL
The crystal X1 should be located as close as possible to the
pins 25 (XTAL_IN) and 26 (XTAL_OUT). The trace length be-
tween the X1 and U1 should be kept to a minimum to avoid
unwanted parasitic inductance and capacitance. Other sig-
nal traces should not be routed near the crystal traces.
F
IGURE
6B. PCB B
OARD
L
AYOUT
FOR
ICS84314-02
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
14
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
Spread-spectrum clocking is a frequency modulation tech-
nique for EMI reduction. When spread-spectrum is enabled,
a 30kHz triangle waveform is used with 0.5% down-spread
(+0.0% / -0.5%) from the nominal 200MHz clock frequency.
An example of a triangle frequency modulation profile is shown
in
Figure 7A
below. The ramp profile can be expressed as:
Fnom = Nominal Clock Frequency in Spread OFF mode
(200MHz with 16MHz IN)
Fm = Nominal Modulation Frequency (30kHz)
= Modulation Factor (0.5% down spread)
(1 -
) fnom + 2 fm x x fnom x t when 0 < t <
,
(1 -
) fnom - 2 fm x x fnom x t when
< t <
1
2 fm
1
2 fm
1
fm
The ICS84314-02 triangle modulation frequency deviation will
not exceed 0.6% down-spread from the nominal clock fre-
quency (+0.0% / -0.5%). An example of the amount of down
spread relative to the nominal clock frequency can be seen in
the frequency domain, as shown in
Figure 7B.
The ratio of
this width to the fundamental frequency is typically 0.4%,
and will not exceed 0.6%. The resulting spectral reduction
will be greater than 7dB, as shown in Figure 7B. It is impor-
tant to note the ICS84314-02 7dB minimum spectral reduc-
tion is the component-specific EMI reduction, and will not
necessarily be the same as the system EMI reduction.
F
IGURE
6B. 200MH
Z
C
LOCK
O
UTPUT
IN
F
REQUENCY
D
OMAIN
(A) S
PREAD
-S
PECTRUM
OFF
(B) S
PREAD
-S
PECTRUM
ON
F
IGURE
6A. T
RIANGLE
F
REQUENCY
M
ODULATION
S
PREAD
S
PECTRUM
Fnom
(1 -
) Fnom
0.5/fm
1/fm
B
A
- 10 dBm
= 0.4%
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
15
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS84314-02 is: 5051
T
ABLE
9.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
16
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EAD
LQFP
T
ABLE
10. P
ACKAGE
D
IMENSIONS
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
3
A
0
6
.
1
1
A
5
0
.
0
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
9
0
.
0
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
0
6
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
0
6
.
5
e
C
I
S
A
B
0
8
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
0
7
c
c
c
0
1
.
0
Reference Document: JEDEC Publication 95, MS-026
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
17
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
11. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
r
e
b
m
u
N
r
e
d
r
O
/
t
r
a
P
g
n
i
k
r
a
M
e
g
a
k
c
a
P
g
n
i
g
a
k
c
a
P
g
n
i
p
p
i
h
S
e
r
u
t
a
r
e
p
m
e
T
2
0
-
Y
A
4
1
3
4
8
S
C
I
2
0
Y
A
4
1
3
4
8
S
C
I
P
F
Q
L
d
a
e
L
2
3
y
a
r
t
C
5
8
o
t
C
0
T
2
0
-
Y
A
4
1
3
4
8
S
C
I
2
0
Y
A
4
1
3
4
8
S
C
I
P
F
Q
L
d
a
e
L
2
3
l
e
e
r
&
e
p
a
t
0
0
0
1
C
5
8
o
t
C
0
F
L
2
0
-
Y
A
4
1
3
4
8
S
C
I
L
2
0
A
4
1
3
4
8
S
C
I
P
F
Q
L
"
e
e
r
F
-
d
a
e
L
"
d
a
e
L
2
3
y
a
r
t
C
5
8
o
t
C
0
T
F
L
2
0
-
Y
A
4
1
3
4
8
S
C
I
L
2
0
A
4
1
3
4
8
S
C
I
P
F
Q
L
"
e
e
r
F
-
d
a
e
L
"
d
a
e
L
2
3
l
e
e
r
&
e
p
a
t
0
0
0
1
C
5
8
o
t
C
0
.
t
n
a
il
p
m
o
c
S
H
o
R
e
r
a
d
n
a
n
o
i
t
a
r
u
g
i
f
n
o
c
e
e
r
F
-
b
P
e
h
t
e
r
a
r
e
b
m
u
n
t
r
a
p
e
h
t
o
t
x
i
f
f
u
s
"
F
L
"
n
a
h
t
i
w
d
e
r
e
d
r
o
e
r
a
t
a
h
t
s
t
r
a
P
:
E
T
O
N
PDF 
ZIP