Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Functional Description
- Pin Descriptions
- Pin Characteristics
- SSC Control Input Function Table
- Programmable VCO Frequency Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Crystal Characteristics
- AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- Cycle-to-Cycle Jitter Diagram
- Output Rise/Fall Time Diagram
- odc & tPeriod Diagram
- Application Information
- Crystal Input and Oscillator Interface
- Crystal Interface Diagram
- Crystal Frequency Plot
- Series Capacitor Plot
- Spread Sprectrum
- Triangle Frequency Modulation Diagram
- 200MHz Clock Output in Frequency Domain Plot
- Power Supply Filtering Techniques
- Power Supply Filtering Diagram
- Termination for LVPECL Outputs
- LVPECL Output Termination Diagrams
- Layout Guideline
- Recommended Schematic Layout
- Power & Grounding
- Clock Traces & Termination
- Crystal
- PCB Board Layout
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
8431EM-11
www.icst.com/products/hiperclocks.html
REV. D JUNE 20, 2003
1
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS8431-11 is a general purpose clock fre-
quency synthesizer for IA64/32 application and
a member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. The VCO
operates at a frequency range of 250MHz to
510MHz providing an output frequency range of 125MHz to
255MHz. The output frequency can be programmed using the
parallel interface, M0 through M8, to the configuration logic.
Spread spectrum clocking is programmed via the control in-
puts SSC_CTL0 and SSC_CTL1.
Programmable features of the ICS8431-11 support four op-
erational modes. The four modes are spread spectrum clock-
ing (SSC), non-spread spectrum clock and two test modes
which are controlled by the SSC_CTL[1:0] pins. Unlike other
synthesizers, the ICS8431-11 can immediately change
spread-spectrum operation without having to reset the device.
In SSC mode, the output clock is modulated in order to achieve
a reduction in EMI. In one of the PLL bypass test modes, the
PLL is disconnected as the source to the differential output
allowing an external source to be connected to the TEST_I/O
pin. This is useful for in-circuit testing and allows the differen-
tial output to be driven at a lower frequency throughout the
system clock tree. In the other PLL bypass mode, the oscilla-
tor divider is used as the source to both the M and the Fout
divide by 2. This is useful for characterizing the oscillator and
internal dividers.
XTAL1
XTAL2
M0:M8
PLL
FOUT
nFOUT
16
TEST_I/O
OSC
VCO
2
PHASE
DETECTOR
M
SSC
Control
Logic
Configuration
Logic
nP_LOAD
SSC_CTL0
F
EATURES
Fully integrated PLL
Differential 3.3V LVPECL output
Crystal oscillator interface
Output frequency range: 125MHz to 255MHz
Crystal input frequency range: 14MHz to 20MHz
VCO range: 250MHz to 510MHz
Programmable PLL loop divider for generating a variety
of output frequencies
Spread Spectrum Clocking (SSC) fixed at 1/2% modulation
for environments requiring ultra low EMI
PLL bypass modes supporting in-circuit testing and on-chip
functional block characterization
Cycle-to-cycle jitter: 30ps (maximum)
3.3V supply voltage
0C to 85C ambient operating temperature
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
SSC_CTL1
M0
M1
M2
M3
M4
M5
M6
M7
M8
SSC_CTL0
SSC_CTL1
V
EE
TEST_I/O
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nP_LOAD
V
CC
XTAL2
XTAL1
nc
nc
V
CCA
V
EE
MR
nc
V
CCO
FOUT
nFOUT
V
EE
ICS8431-11
28-Lead SOIC
7.5mm x 18.05mm x 2.25mm package body
M Package
Top View
HiPerClockSTM
,&6
8431EM-11
www.icst.com/products/hiperclocks.html
REV. D JUNE 20, 2003
2
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
The PLL loop divider or M divider is programmed by using
inputs M0 through M8. While the nP_LOAD input is held LOW,
the data present at M0:M8 is transparent to the M divider. On
the LOW-to-HIGH transition of nP_LOAD, the M0:M8 data is
latched into the M divider and any further changes at the
M0:M8 inputs will not be seen by the M divider until the next
LOW transition on nP_LOAD.
The relationship between the VCO frequency, the crystal fre-
quency and the M divider is defined as follows:
The M value and the required values of M0:M8 for programming
the VCO are shown in
Table 3B, Programmable VCO Frequency
Function Table. The frequency out is defined as follows:
For the ICS8431-11, the output divider equals 2. Valid M val-
ues for which the PLL will achieve lock are defined as:
250
M
510.
F
UNCTIONAL
D
ESCRIPTION
The ICS8431-11 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
A 16MHz series-resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is di-
vided by 16 prior to the phase detector. With a 16MHz crystal this
provides a 1MHz reference frequency. The VCO of the PLL oper-
ates over a range of 250MHz to 510MHz. The output of the M
divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (ei-
ther too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
the LVPECL output buffer. The divider provides a 50% output
duty cycle.
The programmable features of the ICS8431-11 support four
output operational modes and a programmable M divider and
output divider. The four output operational modes are spread
spectrum clocking (SSC), non-spread spectrum clock and
two test modes and are controlled by the SSC_CTL[1:0] pins.
16
M
fVCO =
fxtal x
2
FOUT =
fVCO
=
32
fxtal x M
8431EM-11
www.icst.com/products/hiperclocks.html
REV. D JUNE 20, 2003
3
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
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8431EM-11
www.icst.com/products/hiperclocks.html
REV. D JUNE 20, 2003
4
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. SSC C
ONTROL
I
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F
UNCTION
T
ABLE
T
ABLE
3B. P
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VCO F
REQUENCY
F
UNCTION
T
ABLE
(NOTE 1)
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8431EM-11
www.icst.com/products/hiperclocks.html
REV. D JUNE 20, 2003
5
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
85C
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
85C
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UPPLY
DC C
HARACTERISTICS
,
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CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
85C
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m
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
46.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
8431EM-11
www.icst.com/products/hiperclocks.html
REV. D JUNE 20, 2003
6
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
85C
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
r
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8431EM-11
www.icst.com/products/hiperclocks.html
REV. D JUNE 20, 2003
7
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
R
ISE
/F
ALL
T
IME
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
V
CC
, V
CCA
, V
CCO
= 2V
odc & t
P
ERIOD
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
V
EE
= -1.3V 0.165V
nFOUT
FOUT
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
FOUT
nFOUT
C
YCLE
-
TO
-C
YCLE
J
ITTER
8431EM-11
www.icst.com/products/hiperclocks.html
REV. D JUNE 20, 2003
8
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
The ICS8431-11 features an internal oscillator that uses an
external quartz crystal as the source of its reference frequency.
A 16MHz crystal divided by 16 before being sent to the phase
detector provides the reference frequency. The oscillator is a
series resonant, multi-vibrator type design. This design provides
better stability and eliminates the need for large on chip capacitors.
Though a series resonant crystal is preferred, a parallel resonant
crystal can be used. A parallel resonant mode crystal used in a
series resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified. A few hundred ppm translates
to KHz inaccuracy. In general computing applications this level
of inaccuracy is irrelevant. If better ppm accuracy is required, an
external capacitor can be added to a parallel resonant crystal in
series to pin 25.
Figure 1A shows how to interface with a crystal.
Figures 1A, 1B, and 1C show various crystal parameters which
are recommended only as guidelines.
Figure 1A shows how to
interface a capacitor with an 18pF parallel resonant crystal.
Fig-
ure 1B shows the capacitor value needed for the optimum ppm
performance over various parallel resonant crystals.
Figure 1C
shows the recommended tuning capacitance for a various par-
allel resonant crystal.
F
IGURE
1A. C
RYSTAL
I
NTERFACE
Optional
XTAL2
(Pin 26, SOIC)
XTAL1
(Pin 25, SOIC)
ICS8431-11
F
IGURE
1B. Recommended tuning capacitance for various
18pF parallel resonant crystals.
F
IGURE
1C. Recommended tuning capacitance for various
18pF parallel resonant crystals.
14.318
15.000
16.667
24.000
19.440
20.000
0
10
20
30
40
50
60
14
15
16
17
18
19
20
21
22
23
24
25
Crystal Frequency (MHz)
S
e
r
i
es
C
apac
itor
, C
1
(
p
F
)
-100
-80
-60
-40
-20
0
20
40
60
80
100
0
10
20
30
40
50
60
Series Capacitor, C1 (pF)
F
r
equency A
ccur
a
cy (
ppm
)
19.44MHz
16MHz
15.00MHz
C
RYSTAL
I
NPUT
AND
O
SCILLATOR
I
NTERFACE
A
PPLICATION
I
NFORMATION
8431EM-11
www.icst.com/products/hiperclocks.html
REV. D JUNE 20, 2003
9
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
Spread-spectrum clocking is a frequency modulation tech-
nique for EMI reduction. When spread-spectrum is enabled, a
30KHz triangle waveform is used with 0.5% down-spread
(+0.0% / -0.5%) from the nominal 200MHz clock frequency.
An example of a triangle frequency modulation profile is shown
in
Figure 2A below. The ramp profile can be expressed as:
Fnom = Nominal Clock Frequency in Spread OFF mode
(200MHz with 16MHz IN)
Fm = Nominal Modulation Frequency (30KHz)
= Modulation Factor (0.5% down spread)
(1 -
) fnom + 2 fm x
x fnom x t when 0 < t <
,
(1 -
) fnom - 2 fm x
x fnom x t when
< t <
1
2 fm
1
2 fm
1
fm
The ICS8431-11 triangle modulation frequency deviation will
not exceed 0.6% down-spread from the nominal clock fre-
quency (+0.0% / -0.5%). An example of the amount of down
spread relative to the nominal clock frequency can be seen in
the frequency domain, as shown in
Figure 2B. The ratio of this
width to the fundamental frequency is typically 0.4%, and will
not exceed 0.6%. The resulting spectral reduction will be
greater than 7dB, as shown in Figure 2B. It is important to
note the ICS8431-11 7dB minimum spectral reduction is the
component-specific EMI reduction, and will not necessarily
be the same as the system EMI reduction.
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8431-11 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO
should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, better power supply iso-
lation is required.
Figure 3 illustrates how a 10
along with a
10
F and a .01
F bypass capacitor should be connected to
each V
CCA
pin.
F
IGURE
2B. 200MH
Z
C
LOCK
O
UTPUT
IN
F
REQUENCY
D
OMAIN
(A) S
PREAD
-S
PECTRUM
OFF
(B) S
PREAD
-S
PECTRUM
ON
F
IGURE
2A. T
RIANGLE
F
REQUENCY
M
ODULATION
F
IGURE
3. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
S
PREAD
S
PECTRUM
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
-
10 dBm
= .4%
B
A
Fnom
(1 -
) Fnom
0.5/fm
1/fm
8431EM-11
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Integrated
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ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
The clock layout topology shown below is typical for
IA64/32 platforms. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
4B. LVPECL O
UTPUT
T
ERMINATION
3.3V
FOUT
FIN
5
2 Z
o
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o
= 50
Z
o
= 50
F
IGURE
4A. LVPECL O
UTPUT
T
ERMINATION
RTT =
1
(V
OH
+ V
OL
/ V
CC
2) 2
Z
o
Z
o
= 50
Z
o
= 50
50
50
RTT
V
CC
-2V
FIN
FOUT
F
IGURE
5A. R
ECOMMENDED
S
CHEMATIC
L
AYOUT
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The schematic of the ICS8431-11 layout example used in this
layout guideline is shown in
Figure 5A. The ICS8431-11 rec-
ommended PCB board layout for this example is shown in
Figure 5B. This layout example is used as a general guide-
VCC
VCC
C4
10uF
IN-
R1
50
VCCA
R1
125
C1
0.1uF
IN+
R2
84
VCC0
C6
0.01uF
TL1
Zo = 50 Ohm
VCC
U1
8431-11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28
27
26
25
M0
M1
M2
M3
M4
M5
M6
M7
M8
SSC_CTL0
SSC_CTL1
VEE
TEST_IO
VCC
VEE
nFOUT
FOUT
VCCO
NC
MR
VEE
VCCA
NC
NC
nP_LOAD
VCC
XTAL1
XTAL2
Termination
B (not shown
in the layout)
R3
50
C3
0.01uF
R5
10
IN+
TL2
Zo = 50 Ohm
C2
0.1uF
X1
R3
125
Termination A
R2
50
IN-
R4
84
L
AYOUT
G
UIDELINE
T
ERMINATION
FOR
LVPECL O
UTPUTS
line. The layout in the actual system will depend on the se-
lected component types, the density of the components, the
density of the traces, and the stack up of the P.C. board.
8431EM-11
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REV. D JUNE 20, 2003
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ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
F
IGURE
5B. PCB B
OARD
L
AYOUT
F
OR
ICS8431-11
R5
VIA
ICS8431-11
C4
IN+
TL1 (50 Ohm)
C6
IN-
R2
R4
R3
VCC
Close to the input
pins of the
receiver
X1
Signals
TL2 (50 Ohm)
R1
C3
C1
C2
GND
U1
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C1, C2, C3, C4, and C6, as
close as possible to the power pins. If space allows, placment of
the decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin generated by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R5, C3, and C4 should be placed as
close to the V
CCA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have same
length.
Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible.
Other termination scheme can also be used but is not shown
in the example.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
25 (XTAL1) and 26 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
8431EM-11
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REV. D JUNE 20, 2003
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Integrated
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ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8431-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8431-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 140mA = 485.1mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 1 * 30.2mW = 30.2mW
Total Power
_MAX
(3.465V, with all outputs switching) = 485.1mW + 30.2mW = 515.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.515W * 39.7C/W = 105.4C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
76.2C/W
60.8C/W
53.2C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2C/W
39.7C/W
36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 7. T
HERMAL
R
ESISTANCE
q
JA
FOR
28-
PIN
SOIC, F
ORCED
C
ONVECTION
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ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
1.0V
(V
CCO_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
6. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
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ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8431-11 is: 5555
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
76.2C/W
60.8C/W
53.2C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2C/W
39.7C/W
36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8431EM-11
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REV. D JUNE 20, 2003
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ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- M S
UFFIX
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-013, MO-119
L
O
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8431EM-11
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REV. D JUNE 20, 2003
16
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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8431EM-11
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REV. D JUNE 20, 2003
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Integrated
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ICS8431-11
255MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
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