Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Crystal Characteristics
- AC Characteristics
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Recommendations for Unused Input and Output Pins
- Termination for 3.3V LVPECL Output
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
843204AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 6, 2006
1
Integrated
Circuit
Systems, Inc.
ICS843204I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
PLL
OSC
4
OSC
25MHz
19.44MHz
PLL
4
622.08MHz
155.52MHz
625MHz
156.25MHz
0
1
0
1
0
1
0
1
G
ENERAL
D
ESCRIPTION
The ICS843204I is a 4 output LVPECL
Synthesizer optimized to generate Gigabit
Ethernet and SONET reference clock fre-
quencies and is a member of the HiPerClocks
TM
family of high performance clock solutions from
ICS. Using a 19.44MHz and 25MHz, 18pF parallel resonant
crystal, 155.52MHz and 156.25MHz frequencies can be
generated. The ICS843204I uses ICS' FemtoClock
TM
low
phase noise VCO technology and can achieve 1ps or lower
typical RMS phase jitter. The ICS843204I is packaged in a
48-pin TSSOP package.
F
EATURES
Four 3.3V LVPECL outputs
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
Supports the following output frequencies: 155.52MHz
and 156.25MHz
VCO range: 560MHz - 680MHz
RMS phase jitter @ 155.52MHz, using a 19.44MHz cryst
al
(12kHz - 13MHz): 0.86ps (typical)
RMS phase jitter @ 156.25MHz, using a 19.44MHz cryst
al
(1.875MHz - 20MHz): 0.52ps (typical)
Full 3.3V supply mode
-40C to 85C ambient operating temperature
Available in both standard and lead-free RoHS
compliant packages
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
ICS843204I
48 Lead TSSOP
6.1mm x 12.5mm x 0.93mm
package body
G Package
Top View
nQA1
QA1
nQA0
QA0
nc
V
CCO
_
A
SELA1
SELA0
PLL_BYPASS_A
nc
nc
nc
nc
XTAL_IN1
XTAL_OUT1
CLK1
IN_SEL_B
PLL_BYPASS_B
V
CCO
_
B
nc
QB0
nQB0
QB1
nQB1
IN_SEL_A
CLK0
XTAL_IN0
XTAL_OUT0
nc
V
EE
OEA0
OEA1
V
CC
V
CCA
nc
nc
SELB0
V
EE
OEB0
OEB1
V
CC
SELB1
V
CCA
nc
nc
nc
nc
nc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
PLL_BYPASS_A
IN_SELA
CLK0
XTAL_IN0
XTAL_OUT0
PLL_BYPASS_B
IN_SELB
CLK1
XTAL_IN1
XTAL_OUT1
SELA1
OEA1
SELA0
OEA0
SELB1
OEB1
SELB0
OEB0
B
LOCK
D
IAGRAM
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843204AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 6, 2006
2
Integrated
Circuit
Systems, Inc.
ICS843204I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
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r
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f
e
r
843204AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 6, 2006
3
Integrated
Circuit
Systems, Inc.
ICS843204I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= 3.3V10%, TA = -40C
TO
85C
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= 3.3V10%, TA = -40C
TO
85C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
58.3C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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1
-
A
843204AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 6, 2006
4
Integrated
Circuit
Systems, Inc.
ICS843204I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= 3.3V10%, TA = -40C
TO
85C
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
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ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= 3.3V10%, TA = -40C
TO
85C
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V
2
-
843204AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 6, 2006
5
Integrated
Circuit
Systems, Inc.
ICS843204I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
QA0, QA1
QB0, QB1
RMS P
HASE
J
ITTER
O
UTPUT
S
KEW
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.33V
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
V
CC
,
V
CCA
, V
CCO_X
V
EE
nQA0, nQA1
nQB0, nQB1
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
t
sk(o)
Qy
Qx
nQy
nQx
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
843204AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 6, 2006
6
Integrated
Circuit
Systems, Inc.
ICS843204I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843204I has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
Figure 2
below were determined using an 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
ICS843204I
C1
33p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843204I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and
V
CCO_x
should be individually connected to the power sup-
ply plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
843204AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 6, 2006
7
Integrated
Circuit
Systems, Inc.
ICS843204I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
outputs are designed to drive 50
transmission lines.
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion.
Figures 3A and 3B
show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
resistor can be tied from XTAL_IN to ground.
CLK I
NPUT
:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the CLK input to
ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
843204AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 6, 2006
8
Integrated
Circuit
Systems, Inc.
ICS843204I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843002 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 10% = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.63V * 125mA = 453.75mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power
_MAX
(3.63V, with all outputs switching) = 453.75mW + 120mW = 573.75mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 52.3C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.574W * 52.3C/W = 115C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
82.6C/W
70.3C/W
63.7C/W
Multi-Layer PCB, JEDEC Standard Test Boards
58.3C/W
52.3C/W
49.9C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
7. T
HERMAL
R
ESISTANCE
JA
FOR
48-
PIN
TSSOP, F
ORCED
C
ONVECTION
843204AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 6, 2006
9
Integrated
Circuit
Systems, Inc.
ICS843204I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 4.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
4. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
843204AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 6, 2006
10
Integrated
Circuit
Systems, Inc.
ICS843204I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843204I is: 4090
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
48 L
EAD
TSSOP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
82.6C/W
70.3C/W
63.7C/W
Multi-Layer PCB, JEDEC Standard Test Boards
58.3C/W
52.3C/W
49.9C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843204AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 6, 2006
11
Integrated
Circuit
Systems, Inc.
ICS843204I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
48 L
EAD
TSSOP
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
m
u
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4
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-
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843204AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 6, 2006
12
Integrated
Circuit
Systems, Inc.
ICS843204I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical
medical instruments.
The aforementioned trademarks, HiPerClockS and F
EMTO
C
LOCKS
are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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