Document Outline
- General Description
- Features
- Common Configuration Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- 3.3V Power Supply DC Characteristics
- 2.5V Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 2.5V AC Characteristics
- Typical Phase Noise Plot
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Termination for 3.3V LVPECL Output
- Termination for 2.5V LVPECL Output
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
843251BGI-12
www.icst.com/products/hiperclocks.html
REV. A JANUARY 10, 2006
1
Integrated
Circuit
Systems, Inc.
ICS843251I-12
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS843251I-12 is a 10Gb Ethernet Clock
Generator and a member of the HiPerClocks
TM
family of high performance devices from ICS. The
ICS843251I-12 uses an 18pF parallel resonant
crystal over the range of 23.2MHz - 30MHz. For
Ethernet applications, a 25MHz crystal is used. The device
has excellent <1ps phase jitter performance, over the
1.875MHz - 20MHz integration range. The ICS843251I-12
is packaged in a small 8-pin TSSOP, making it ideal for
use in systems with limited board space.
F
EATURES
One Differential LVPECL output
Crystal oscillator interface, 18pF parallel resonant crystal
(23.2MHz - 30MHz)
Output frequency range: 290MHz - 750MHz
VCO range: 580MHz - 750MHz
RMS phase jitter @ 312.5MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.36ps (typical)
3.3V or 2.5V operating supply
-40C to 85C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
HiPerClockSTM
ICS
ICS843251I-12
8-Lead TSSOP
4.4mm x 3.0mm x 0.925mm
package body
G Package
Top View
V
CCA
V
EE
XTAL_OUT
XTAL_IN
1
2
3
4
V
CC
Q
nQ
FREQ_SEL
8
7
6
5
B
LOCK
D
IAGRAM
OSC
Phase
Detector
VCO
580MHz - 750MHz
M = 25
(fixed)
FREQ_SEL N
0 1
1 2
Pullup
XTAL_IN
XTAL_OUT
Q
nQ
C
OMMON
C
ONFIGURATION
T
ABLE
P
IN
A
SSIGNMENT
FREQ_SEL
s
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5
.
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5
.
2
1
3
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843251BGI-12
www.icst.com/products/hiperclocks.html
REV. A JANUARY 10, 2006
2
Integrated
Circuit
Systems, Inc.
ICS843251I-12
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
1. P
IN
D
ESCRIPTIONS
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843251BGI-12
www.icst.com/products/hiperclocks.html
REV. A JANUARY 10, 2006
3
Integrated
Circuit
Systems, Inc.
ICS843251I-12
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, T
A
= -40C
TO
85C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
101.7C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%
OR
2.5V5%, T
A
= -40C
TO
85C
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 2.5V5%, T
A
= -40C
TO
85C
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843251BGI-12
www.icst.com/products/hiperclocks.html
REV. A JANUARY 10, 2006
4
Integrated
Circuit
Systems, Inc.
ICS843251I-12
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
T
ABLE
5A. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
5B. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= 2.5V5%, T
A
= -40C
TO
85C
T
ABLE
3D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%
OR
2.5V5%, T
A
= -40C
TO
85C
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T
O
N
843251BGI-12
www.icst.com/products/hiperclocks.html
REV. A JANUARY 10, 2006
5
Integrated
Circuit
Systems, Inc.
ICS843251I-12
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
AT
312.5MH
Z
(3.3V)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
O
FFSET
F
REQUENCY
dBc
Hz
N
OISE
P
OWER
312.5MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.36ps (typical)
Phase Noise Result by adding
10GigE Filter to raw data
Raw Phase Noise Data
10GigE Filter
843251BGI-12
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REV. A JANUARY 10, 2006
6
Integrated
Circuit
Systems, Inc.
ICS843251I-12
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
RMS P
HASE
J
ITTER
LVPECL 3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
LVPECL 2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q
nQ
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.165V
V
EE
V
CC,
V
CCA
SCOPE
Qx
nQx
LVPECL
2V
-0.5V 0.125V
V
EE
V
CC,
V
CCA
843251BGI-12
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REV. A JANUARY 10, 2006
7
Integrated
Circuit
Systems, Inc.
ICS843251I-12
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
A
PPLICATION
I
NFORMATION
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843251I-12 has been characterized with 18pF par-
allel resonant crystals. The capacitor values (TBD), C1 and
C2, shown in
Figure 2
below were determined using a
25MHz, 18pF parallel resonant crystal and were chosen to
minimize the ppm error. The optimum C1 and C2 values
can be slightly adjusted for different board layouts.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843251I-12 pro-
vides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. V
CC
and V
CCA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
pin. The 10
resistor can also be replaced by a ferrite bead.
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
CC
10
F
.01
F
3.3V or 2.5V
.01
F
V
CC
C1
X1
Crystal
C2
XTAL_IN
XTAL_OUT
843251BGI-12
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REV. A JANUARY 10, 2006
8
Integrated
Circuit
Systems, Inc.
ICS843251I-12
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
designed to drive 50
transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion.
Figures 3A and
3B
show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.
843251BGI-12
www.icst.com/products/hiperclocks.html
REV. A JANUARY 10, 2006
9
Integrated
Circuit
Systems, Inc.
ICS843251I-12
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 4A
and
Figure 4B
show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very close to
ground level. The R3 in Figure 4B can be eliminated and the
termination is shown in
Figure 4C.
F
IGURE
4C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
F
IGURE
4B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
F
IGURE
4A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
Zo = 50 Ohm
R1
250
+
-
2.5V
2,5V LVPECL
Driv er
R4
62.5
R3
250
Zo = 50 Ohm
2.5V
VCC=2.5V
R1
50
R3
18
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
VCC=2.5V
2.5V
R2
50
2,5V LVPECL
Driv er
VCC=2.5V
R1
50
R2
50
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
+
-
843251BGI-12
www.icst.com/products/hiperclocks.html
REV. A JANUARY 10, 2006
10
Integrated
Circuit
Systems, Inc.
ICS843251I-12
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843251I-12 is: 2377
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
843251BGI-12
www.icst.com/products/hiperclocks.html
REV. A JANUARY 10, 2006
11
Integrated
Circuit
Systems, Inc.
ICS843251I-12
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
8 L
EAD
TSSOP
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
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s
r
e
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m
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843251BGI-12
www.icst.com/products/hiperclocks.html
REV. A JANUARY 10, 2006
12
Integrated
Circuit
Systems, Inc.
ICS843251I-12
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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PDF 
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