843252AG-04
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
1
Integrated
Circuit
Systems, Inc.
ICS843252-04
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS843252-04 is a 10Gb/12Gb Ethernet
Clock Generator and a member of the
HiPerClocks
TM
family of high perfor mance
devices from ICS. The ICS843252-04 can
synthesize 10 Gigabit Ethernet and 12 Gigabit
Ethernet with a 25MHz crystal. It can also generate SATA
and 10Gb Fibre Channel reference clock frequencies with
the appropriate choice of crystals. The ICS843252-04 has
excellent phase jitter performance and is packaged in a
small 16-pin TSSOP, making it ideal for use in systems with
limited board space.
F
EATURES
Two differential 3.3V LVPECL output
Crystal oscillator interface designed for
18pF parallel resonant crystals
Crystal input frequency range: 19.33MHz - 30MHz
Output frequency range: 145MHz - 187.5MHz
VCO frequency range: 580MHz - 750MHz
RMS phase jitter at 156.25MHz (1.875MHz - 20MHz):
0.39ps (typical)
3.3V operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
Available in both standard and lead-free compliant
packages
HiPerClockSTM
ICS
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
1
0
1
0
Phase
Detector
VCO
580MHz-750MHz
OSC
0 = 25
(default)
1 = 30
DIV. N
4
D
LE
Q
XTAL_IN
XTAL_OUT
Q0
nQ0
Q1
nQ1
FREQ_SEL
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LOCK
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CLK_SEL
REF_CLK
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OE
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CCO
OE
nPLL_SEL
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CCO
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XTAL_IN
XTAL_OUT
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EE
REF_CLK
CLK_SEL
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CC
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CCA
FREQ_SEL
ICS843252-04
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843252AG-04
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
2
Integrated
Circuit
Systems, Inc.
ICS843252-04
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
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843252AG-04
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
3
Integrated
Circuit
Systems, Inc.
ICS843252-04
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
89C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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843252AG-04
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
4
Integrated
Circuit
Systems, Inc.
ICS843252-04
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
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843252AG-04
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
5
Integrated
Circuit
Systems, Inc.
ICS843252-04
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
S
KEW
O
UTPUT
R
ISE
/F
ALL
T
IME
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.165V
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q0, Q1
nQ0, nQ1
V
EE
V
CC,
V
CCA,
V
CCO
RMS P
HASE
J
ITTER
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
t
sk(o)
nQy
Qy
nQx
Qx
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
PDF 
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