Document Outline
- General Description
- Features
- Select Function Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Crystal Function Table
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- Power Supply 3.3V/2.5V DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- Typical Phase Noise Plots
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Recommendations for Unused Input and Output Pins
- Termination for 3.3V LVPECL Output
- Termination for 2.5V LVPECL Output
- Reliability Information
- Transistor Count
- Package Outline for 24 Lead SOIC
- Package Dimensions for 24 Lead SOIC
- Package Outline for 24 Lead TSSOP
- Package Dimensions for 24 Lead TSSOP
- Ordering Information Table
843256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
1
Integrated
Circuit
Systems, Inc.
ICS843256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS843256 is a Crystal-to-3.3V LVPECL
Clock Synthesizer/Fanout Buffer designed for
Fibre Channel and Gigabit Ethernet applications
and is a member of the HiperClockSTM family of
High Performance Clock Solutions from ICS. The
output frequency can be set using the frequency select
pins and a 25MHz crystal for Ethernet frequencies, or a
19.44MHz crystal for SONET. The low phase noise charac-
teristics of the ICS843256 make it an ideal clock for these
demanding applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Six LVPECL outputs
Crystal oscillator interface
Output frequency range: 53.125MHz to 333.3333MHz
Crystal input frequency range: 25MHz to 33.333MHz
RMS phase jitter at 125MHz, using a 25MHz crystal
(1.875MHz to 20MHz): 0.33ps (typical)
Full 3.3V or 3.3V core, 2.5V output supply mode
0C to 70C ambient operating temperature
Industrial temperature information available upon request
Available in both standard and lead-free RoHS-compliant
packages
HiPerClockSTM
ICS
Q0
ICS843256
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm
body package
M Package
Top View
V
CCO
V
CCO
nQ2
Q2
nQ1
Q1
nQ0
Q0
PLL_BYPASS
V
CCA
V
CC
FB_SEL
1
2
3
4
5
6
7
8
9
10
11
12
Q3
nQ3
Q4
nQ4
Q5
nQ5
N_SEL1
V
EE
V
EE
N_SEL0
XTAL_OUT
XTAL_IN
OSC
PLL
Feedback
Divider
Output
Divider
1
0
XTAL_IN
XTAL_OUT
PLL_BYPASS
nQ0
24
23
22
21
20
19
18
17
16
15
14
13
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
FB_SEL
N_SEL1
N_SEL0
Pullup
Pulldown
Pullup
Pullup
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
body package
G Package
Top View
S
ELECT
F
UNCTION
T
ABLE
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8
4
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
2
Integrated
Circuit
Systems, Inc.
ICS843256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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843256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
3
Integrated
Circuit
Systems, Inc.
ICS843256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
3. C
RYSTAL
F
UNCTION
T
ABLE
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843256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
4
Integrated
Circuit
Systems, Inc.
ICS843256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO
= 3.3V5%
OR
2.5V5%, T
A
= 0C
TO
70C
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO
= 2.5V5%, T
A
= 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
24 Lead SOIC
50C/W (0 lfpm)
24 Lead TSSOP
70C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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843256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
5
Integrated
Circuit
Systems, Inc.
ICS843256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
T
ABLE
6A. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
6B. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO
= 2.5V5%, T
A
= 0C
TO
70C
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO
= 3.3V5%
OR
2.5V5%, T
A
= 0C
TO
70C
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843256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
6
Integrated
Circuit
Systems, Inc.
ICS843256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
AT
125MH
Z
@ 3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.33ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
OWER
dBc
Hz
Phase Noise Result by adding
Ethernet Filter to raw data
Raw Phase Noise Data
Ethernet Filter
10
100
1k
10k
100k
1M
10M
100M
T
YPICAL
P
HASE
N
OISE
AT
125MH
Z
@ 3.3V/2.5V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.32ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
OWER
dBc
Hz
Phase Noise Result by adding
Ethernet Filter to raw data
Raw Phase Noise Data
Ethernet Filter
10
100
1k
10k
100k
1M
10M
100M
843256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
7
Integrated
Circuit
Systems, Inc.
ICS843256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
nQ0:nQ5
Q0:Q5
t
sk(o)
nQx
Qx
nQy
Qy
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.165V
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
S
KEW
SCOPE
Qx
nQx
LVPECL
V
CCO
-0.5V 0.125V
2V
V
CC
,
V
CCA
2.8V0.04V
V
EE
V
CC
,
V
CCA
, V
CCO
V
EE
843256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
8
Integrated
Circuit
Systems, Inc.
ICS843256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843256 provides sepa-
r a t e p o w e r s u p p l i e s t o i s o l a t e a n y h i g h s w i t c h i n g
noise from the outputs to the internal PLL. V
CC
, V
CCA
and V
CCO
should be individually connected to the power supply plane
through vias, and bypass capacitors should be used for each
pin. To achieve optimum jitter performance, power supply iso-
lation is required.
Figure 1
illustrates how a 10
resistor along
with a 10
F and a .01F bypass capacitor should be con-
nected to each V
CCA
pin. The 10
resistor can also be re-
placed by a ferrite bead.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
A
PPLICATION
I
NFORMATION
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843256 has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in
Figure 2
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
below were determined using an 18pF parallel resonant
crystal and were chosen to minimize the ppm error.
C1
18p
X1
18pF Parallel Crystal
C2
22p
XTAL_IN
XTAL_OUT
843256AM
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REV. A NOVEMBER 29, 2005
9
Integrated
Circuit
Systems, Inc.
ICS843256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
designed to drive 50
transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion.
Figures 3A and
3B
show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate to
guarantee compatibility across all printed circuit and clock
component process variations.
I
NPUTS
:
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
843256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
10
Integrated
Circuit
Systems, Inc.
ICS843256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 4A
and
Figure 4B
show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to
terminating 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very
close to ground level. The R3 in Figure 4B can be eliminated
and the termination is shown in
Figure 4C.
F
IGURE
4C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driv er
F
IGURE
4B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driv er
Zo = 50 Ohm
+
-
2.5V
F
IGURE
4A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driv er
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
843256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
11
Integrated
Circuit
Systems, Inc.
ICS843256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843256 is: 3863
T
ABLE
7A.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
S
OIC
JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
50C/W
43C/W
38C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
7B.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
843256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
12
Integrated
Circuit
Systems, Inc.
ICS843256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
P
ACKAGE
O
UTLINE
- M S
UFFIX
FOR
24 L
EAD
SOIC
T
ABLE
8A. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-013, MO-119
L
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ACKAGE
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UTLINE
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ABLE
8B. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
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843256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
13
Integrated
Circuit
Systems, Inc.
ICS843256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockS and F
EMTO
C
LOCKS
are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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