Document Outline
- General Description
- Features
- Function Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Crystal Characteristics
- AC Characteristics
- Typical Phase Noise Plots
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- Output Skew Diagram
- Output Duty Cyle/Pulse Width/Period Diagram
- Output Rise/Fall Time Diagram
- Application Information
- Power Supply Filtering Techniques
- Power Supply Filtering Diagram
- Termination for LVPECL Outputs
- LVPECL Output Termination Diagrams
- Crystal Input Interface
- Schematic Example
- Power & Grounding
- Clock Traces & Termination
- Crystal
- PCB Board Layout
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
84325EM
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
1
Integrated
Circuit
Systems, Inc.
ICS84325
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS84325 is a Crystal-to-3.3V LVPECL
Frequency Synthesizer with Fanout Buffer and a
member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. The
output frequency can be programmed using
frequency select pins. The low phase noise characteristics
of the ICS84325 make it an ideal clock source for Fibre
Channel 1, Fibre Channel 2, Infiniband and Gigabit
Ethernet applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
6 differential 3.3V LVPECL outputs
Crystal oscillator interface
Output frequency range: 106.25MHz to 250MHz
Crystal input frequency: 25MHz and 25.5MHz
Output skew: 60ps (maximum)
RMS phase jitter at 212.5MHz, using a 25.5MHz crystal
(637KHz to 10MHz): 2.76ps
Phase noise: Typical at 212.5MHz
Offset
Noise Power
100Hz ................. -92 dBc/Hz
1KHz ................. -112 dBc/Hz
10KHz ................. -120 dBc/Hz
100KHz ................. -122 dBc/Hz
3.3V supply voltage
0C to 70C ambient operating temperature
Lead-Free package available.
Industrial temperature information available upon request
HiPerClockSTM
ICS
Q0:Q5
ICS84325
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
Top View
Q0
nQ0
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Q2
nQ2
Q3
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Q4
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Q5
nQ5
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CCO
F_SEL0
F_SEL1
MR
XTAL1
XTAL2
V
EE
V
CCA
V
CC
PLL_SEL
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EE
V
CCO
PLL
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OSC
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0
1
6
/
6
/
XTAL1
XTAL2
F_SEL1
PLL_SEL
MR
F_SEL0
nQ0:nQ5
F
UNCTION
T
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84325EM
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
2
Integrated
Circuit
Systems, Inc.
ICS84325
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
T
ABLE
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IN
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84325EM
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
3
Integrated
Circuit
Systems, Inc.
ICS84325
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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HARACTERISTICS
,
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-
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
50C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
84325EM
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
4
Integrated
Circuit
Systems, Inc.
ICS84325
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
r
e
t
e
m
a
r
a
P
s
n
o
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t
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t
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T
m
u
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i
n
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M
l
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p
y
T
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x
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t
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y
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q
e
r
F
5
2
5
.
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M
)
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S
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c
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=
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=
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%
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H
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5
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2
1
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=
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%
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H
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=
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t
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:
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d
r
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p
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h
T
:
2
E
T
O
N
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
84325EM
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
5
Integrated
Circuit
Systems, Inc.
ICS84325
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
T
YPICAL
P
HASE
N
OISE
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
P
HASE
N
OISE
(
dBc
)
H
Z
Jitter BW
Jitter Filter
Diff. Jitter
Source
Mode
Process Result
Noise only
Freq. carrier
Start Freq.
Stop Freq.
Jitter
10.000
40.000M Hz
2.76 ps
212.500M Hz
Fibre Channel 2
Bandpass Filter
Raw phase noise data
Phase noise result by adding
Bandpass Filter to raw data
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
O
FFSET
F
REQUENCY
(H
Z
)
P
HASE
N
OISE
(
dBc
)
H
Z
Jitter BW
Jitter Filter
Diff. Jitter
Source
Mode
Process Result
Noise only
Freq. carrier
Start Freq.
Stop Freq.
Jitter
10.000
40.000M Hz
2.62 ps
106.250M Hz
Fibre Channel 1
Bandpass Filter
Raw phase noise data
Phase noise result by adding
Bandpass Filter to raw data
100
1k
10k
100k
1M
10M
100M
84325EM
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
6
Integrated
Circuit
Systems, Inc.
ICS84325
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
S
KEW
SCOPE
Qx
nQx
LVPECL
t
sk(o)
Qy
Qx
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
Q0:Q5
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
P
ARAMETER
M
EASUREMENT
I
NFORMATION
nQ0:nQ5
2V
-1.3V 0.165V
nQy
nQx
V
EE
V
CC,
V
CCA
84325EM
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REV. B OCTOBER 11, 2004
7
Integrated
Circuit
Systems, Inc.
ICS84325
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84325 provides sepa-
r a t e p o w e r s u p p l i e s t o i s o l a t e a n y h i g h s w i t c h i n g
noise from the outputs to the internal PLL. V
CC
, V
CCA
and V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2 illustrates how
a 24
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
24
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
84325EM
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REV. B OCTOBER 11, 2004
8
Integrated
Circuit
Systems, Inc.
ICS84325
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
S
CHEMATIC
E
XAMPLE
Figure 5A shows a schematic example of using an ICS84325. In
this example, the input is a 25MHz parallel resonant crystal with
load capacitor CL=18pF. The frequency fine tuning capacitors
C1 and C2 are 22pF respectively. This example also shows logic
control input handling. The configuration is set at F_SEL[1:0]=11
F
IGURE
5A. ICS84325 S
CHEMATIC
E
XAMPLE
therefore the output frequency is 250MHz. It is recommended to
have one decouple capacitor per power pin. Each decoupling
capacitor should be located as close as possible to the power
pin. The low pass filter R7, C11 and C16 for clean analog supply
should also be located as close to the V
CCA
pin as possible.
Figure 4. C
RYSTAL
I
NPU
t I
NTERFACE
were chosen to minimize the ppm error. The optimum C1 and C2
values can be slightly adjusted for different board layouts.
C1
22p
X1
18pF Parallel Cry stal
C2
22p
XTAL2
XTAL1
R1
50
R3
50
R4
1K
Zo = 50
C6
0.1u
C1
22p
RD3
SP
Zo = 50
C5
0.1u
VCC
C16
10u
RU3
1K
C3
0.1u
VCC
C2
22p
U7
ICS84325
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
VCC
VEE
PLL_SEL
VCC
VCCA
VEE
XTAL2
XTAL1
MR
F_SEL1
F_SEL0
VCC
X1
25MHz,18pF
SP = Spare, Not Installed
R5
1K
RD2
SP
C11
0.1u
VCC
e.g. F_SEL[1:0]=11
(U1,16)
VCCA
(U1,13)
F_SEL1
(U1,24)
F_SEL0
F_SEL1
VCC
VCC
F_SEL0
VCC=3.3V
+
-
R7
24
R2
50
RU2
1K
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS84325 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in
Figure 3 below
were determined using a 25MHz, 18pF parallel resonant crystal and
84325EM
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REV. B OCTOBER 11, 2004
9
Integrated
Circuit
Systems, Inc.
ICS84325
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
50 Ohm Traces
C1
C3
C5
GND
VCCA
ICS84325
U1
C11
C16
Signals
VCC
C6
C2
R7
VIA
X1
Pin1
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C3, C5 and C6, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
DDA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 100
output traces should have the
same length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
20 (XTAL1) and 19 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
F
IGURE
5B. PCB B
OARD
L
AYOUT
FOR
ICS84325
84325EM
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REV. B OCTOBER 11, 2004
10
Integrated
Circuit
Systems, Inc.
ICS84325
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84325.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84325 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 210mA = 727.7mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30.2mW = 181mW
Total Power
_MAX
(3.465V, with all outputs switching) = 727.7mW + 181mW = 908.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.909W * 43C/W = 113.9C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
50C/W
43C/W
38C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
6. T
HERMAL
R
ESISTANCE
JA
FOR
24-
PIN
SOIC, F
ORCED
C
ONVECTION
84325EM
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REV. B OCTOBER 11, 2004
11
Integrated
Circuit
Systems, Inc.
ICS84325
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
1.0V
(V
CCO_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
) * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
6. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
84325EM
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REV. B OCTOBER 11, 2004
12
Integrated
Circuit
Systems, Inc.
ICS84325
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS84325 is: 3500
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
SOIC
JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
50C/W
43C/W
38C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
84325EM
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
13
Integrated
Circuit
Systems, Inc.
ICS84325
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- M S
UFFIX
FOR
24 L
EAD
SOIC
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-013, MO-119
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
m
u
m
i
n
i
M
m
u
m
i
x
a
M
N
4
2
A
-
-
5
6
.
2
1
A
0
1
.
0
-
-
2
A
5
0
.
2
5
5
.
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www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
14
Integrated
Circuit
Systems, Inc.
ICS84325
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While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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84325EM
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
15
Integrated
Circuit
Systems, Inc.
ICS84325
C
RYSTAL
-
TO
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REQUENCY
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YNTHESIZER
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