Document Outline
- General Description
- Features
- Function Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- LVCMOS 3.3V DC Characteristics
- LVPECL 3.3V DC Characteristics
- Power Supply 3.3V/2.5V DC Characteristics
- LVCMOS 3.3V/2.5V DC Characteristics
- LVPECL 3.3V/2.5V DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- 3.3V/2.5V Output Load AC Test Circuit Diagram
- Output Skew Diagram
- Period Jitter Diagram
- Cycle-to-Cycle Jitter Diagram
- Output Rise/Fall Time Diagram
- odc & tPeriod Diagram
- Applications Information
- Power Supply Filtering Techniques
- Power Supply Filtering Diagram
- Terminatin for 3.3V LVPECL Outputs
- LVPECL 3.3V Output Termination Diagrams
- Terminatin for 2.5V LVPECL Outputs
- LVPECL 2.5V Output Termination Diagrams
- Crystal Input Interface
- Crystal Input Interface Diagrams
- Schematic Example
- Power & Grounding
- Clock Traces & Termination
- Crystal
- PC Board Layout
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
84326AM
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2003
1
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS84326 is a Crystal-to-3.3V LVPECL Clock
Synthesizer/Fanout Buffer designed for Serial
Attached SCSI applications and is a member of
the HiperClockS family of High Performance Clock
Solutions from ICS. Using a 25MHz crystal, the
6 LVPECL outputs can be set for either 75MHz or 150MHz
using the frequency select pins. The low jitter/low phase noise
characteristics make it an ideal clock source for use in Serial
Attached SCSI applications or for other applications which
require a 75MHz or 150MHz reference clock.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
6 LVPECL outputs
Crystal oscillator interface
Output frequency: 75MHz or 150MHz
Crystal input frequency: 25MHz
Cycle-to-cycle jitter: 20ps (typical)
RMS phase jitter at 150MHz, using a 25MHz crystal
(899.8KHz to 20MHz): TBD
Phase noise:
Offset
Noise Power
100Hz ............... TBD
1KHz ............... TBD
10KHz ............... TBD
100KHz ............... TBD
Full 3.3V or 3.3V core, 2.5V supply mode
0C to 70C ambient operating temperature
Industrial temperature information available upon request
HiPerClockSTM
,&6
Q0:Q5
ICS84326
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
Top View
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
1
2
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6
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8
9
10
11
12
V
CCO
F_SEL
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MR
XTAL1
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CCA
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CC
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EE
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CCO
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6
/
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OSC
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/
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UNCTION
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ABLE
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M
5
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0
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z
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M
0
5
1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84326AM
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2003
2
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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84326AM
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2003
3
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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-
A
T
ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, V
O
-0.5V to V
CCO
+ 0.5V
Package Thermal Impedance,
JA
50C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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:
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E
T
O
N
V
o
t
O
C
C
.
V
2
-
84326AM
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2003
4
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
r
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3E. LVCMOS / LVTTL DC C
HARACTERISTICS
,
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CC
= V
CCA
= 3.3V5%, V
CCO
= 2.5V5%, T
A
= 0C
TO
70C
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-
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T
ABLE
3F. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO
= 2.5V5%, T
A
= 0C
TO
70C
T
ABLE
3D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO
= 2.5V5%, T
A
= 0C
TO
70C
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C
.
V
2
-
84326AM
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2003
5
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
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5A. AC C
HARACTERISTICS
,
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ABLE
5B. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO
= 2.5V5%, T
A
= 0C
TO
70C
84326AM
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2003
6
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
odc & t
P
ERIOD
C
YCLE
-
TO
-C
YCLE
J
ITTER
O
UTPUT
R
ISE
/F
ALL
T
IME
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
contains 68.26% of all measurements
2
contains 95.4% of all measurements
3
contains 99.73% of all measurements
4
contains 99.99366% of all measurements
6
contains (100-1.973x10
-7
)% of all measurements
Histogram
Clock Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
nQ0:nQ5
Q0:Q5
nQ0:nQ5
Q0:Q5
tsk(o)
nQx
Qx
nQy
Qy
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
V
CC
, V
CCA
, V
CCO
= 2V
V
EE
= -1.3V 0.165V
P
ERIOD
J
ITTER
O
UTPUT
S
KEW
SCOPE
Qx
nQx
LVPECL
V
CCO
V
EE
= -0.5V 0.165V
2V
2.8V
V
CC
,
V
CCA
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
84326AM
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2003
7
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84326 provides sepa-
r a t e p o w e r s u p p l i e s t o i s o l a t e a n y h i g h s w i t c h i n g
noise from the outputs to the internal PLL. V
CC
, V
CCA
and V
CCO
should be individually connected to the power supply plane
through vias, and bypass capacitors should be used for each
pin. To achieve optimum jitter performance, power supply iso-
lation is required.
Figure 1 illustrates how a 20
resistor along
with a 10
F and a .01
F bypass capacitor should be con-
nected to each V
CCA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
20
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
A
PPLICATION
I
NFORMATION
T
ERMINATION
FOR
3.3V LVPECL O
UTPUTS
The clock layout topology shown below is a typical termina-
tion for 3.3V LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
3.3V
F
OUT
F
IN
5
2 Z
o
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o
= 50
Z
o
= 50
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
RTT =
1
(V
OH
+ V
OL
/ V
CC
2) 2
Z
o
Z
o
= 50
Z
o
= 50
50
50
RTT
V
CC
- 2V
F
IN
F
OUT
designed to drive 50
transmission lines. Matched impedance
t e c h n i q u e s s h o u l d b e u s e d t o m a x i m i z e o p e r a t i n g
frequency and minimize signal distortion.
Figures 2A and 2B
show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate to
guarantee compatibility across all printed circuit and clock
component process variations.
84326AM
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2003
8
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
2.5V
Zo = 50 Ohm
R3
18
+
-
Zo = 50 Ohm
2.5V
R2
50
R1
50
2,5V LVPECL
Driver
R3
250
+
-
2.5V
2,5V LVPECL
Driver
2.5V
Zo = 50 Ohm
R4
62.5
R2
62.5
2.5V
Zo = 50 Ohm
R1
250
2.5V
R1
50
R2
50
+
-
Zo = 50 Ohm
2.5V
2,5V LVPECL
Driver
Zo = 50 Ohm
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very close to
ground level. The R3 in Figure 3B can be eliminated and the
termination is shown in
Figure 3C.
F
IGURE
3A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
F
IGURE
3B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
F
IGURE
3C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
84326AM
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REV. A MARCH 10, 2003
9
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
F
IGURE
5A. ICS84326 S
CHEMATIC
E
XAMPLE
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS84326 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown
in
Figure 4 below were determined using a 25MHz, 18pF
Figure 4. C
RYSTAL
I
NPU
t I
NTERFACE
C2
22pF
C1
18pF
25MHz X1
ICS84326
19
20
XTAL2
XTAL1
parallel resonant crystal and were chosen to minimize the
ppm error. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
S
CHEMATIC
E
XAMPLE
Figure 5A shows a schematic example of using an ICS84326. In
this example, the input is a 25MHz parallel resonant crystal with
load capacitor CL=18pF. The frequency fine tuning capacitors C1
and C2 is 22pF and 18pF respectively. This example also shows
logic control input handling. The configuration is set at F_SEL=0,
therefore, the output frequency is 150MHz. It is recommended to
have one decouple capacitor per power pin. Each decoupling ca-
pacitor should be located as close as possible to the power pin.
The low pass filter R7, C11 and C16 for clean analog supply should
also be located as close to the V
CCA
pin as possible.
X1
25MHz,18pF
C5
0.1u
R6
1K
VCCA
R2
50
VCC
+
-
R5
1K
VCC
R3
50
VCC=3.3V
U1
ICS84326
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
VCCO
VEE
PLL_SEL
VCC
VCCA
nc
XTAL2
XTAL1
MR
nc
F_SEL
VCCO
(U1,24)
C6
0.1u
C 16
10u
VCC
(U1,13)
C2
18p
VCC
R7
24
R1
50
C11
0.1u
Zo = 50
Zo = 50
R4
1K
(U 1,16)
C3
0.1u
C1
22p
84326AM
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REV. A MARCH 10, 2003
10
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
ICS84326
R7
VIA
C1
VCC
GND
C11
C2
C16
U1
C5
Pin1
X1
C6
50 Ohm Traces
C3
Signals
F
IGURE
5B. ICS84326 P.C. B
OARD
L
AYOUT
E
XAMPLE
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C5, C6 and C3, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
CCA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have the
same length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
20 (XTAL1) and 19 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
84326AM
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REV. A MARCH 10, 2003
11
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84326.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84326 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 140mA = 485mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30.2mW = 181mW
Total Power
_MAX
(3.465V, with all outputs switching) = 485mW + 181mW = 666mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.666W * 43C/W = 98.6C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
T
ABLE
6. T
HERMAL
R
ESISTANCE
q
JA
FOR
24-P
IN
SOIC, F
ORCED
C
ONVECTION
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
50C/W
43C/W
38C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
84326AM
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REV. A MARCH 10, 2003
12
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
1.0V
(V
CCO_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
6. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
84326AM
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REV. A MARCH 10, 2003
13
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS84326 is: 2804
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
50C/W
43C/W
38C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
84326AM
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2003
14
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
P
ACKAGE
O
UTLINE
- M S
UFFIX
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-013, MO-119
L
O
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Y
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r
e
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84326AM
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REV. A MARCH 10, 2003
15
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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