Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignments
- Functional Description
- Parallel & Serial Load Operations Diagram
- Pin Descriptions
- Pin Characteristics
- Parallel & Serial Mode Function Table
- Programmable VCO Frequency Function Table
- Programmable Output Divider Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Crystal Characteristics
- Input Frequency Characteristics
- AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- Cycle-to-Cycle Jitter Diagram
- Period Jitter Diagram
- odc & tPeriod Diagram
- Output Rise/Fall Time Diagram
- Setup & Hold Diagram
- Application Information
- Power Supply Filtering Techniques
- Power Supply Filtering Diagram
- Termination for LVPECL Outputs
- LVPECL Output Termination Diagrams
- RMS Jitter vs. fOUT Plot
- Cycle-to-Cycle Jitter vs. fOUT Plot
- Crystal Input & Oscillator Interface
- Crystal Interface Diagram
- Series Resonant Crystal Frequency Plot
- Layout Guideline
- Schematic of Recommended Layout
- Power & Grounding
- Clock Traces & Termination
- Crystal
- PCB Board Layout
- Power Considerations
- Power Dissipation
- Thermal Resistance for 28 pin PLCC
- Thermal Resistance for 32 pin LQFP
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- PLCC Package Outline
- PLCC Package Dimensions
- TQFP Package Outline
- TQFP Package Dimensions
- Ordering Information
- Revsion History Sheet
84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
1
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS84329 is a general purpose, single output
high frequency synthesizer and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The VCO operates at a fre-
quency range of 200MHz to 700MHz. The VCO
frequency is programmed in steps equal to the value of the
crystal frequency divided by 16. The VCO and output frequency
can be programmed using the serial or parallel interfaces to the
configuration logic. The output can be configured to divide the
VCO frequency by 1, 2, 4, and 8. Output frequency steps as
small as 125KHz to 1MHz can be achieved using a 16MHz
crystal depending on the output dividers.
F
EATURES
Fully integrated PLL, no external loop filter requirements
1 differential 3.3V LVPECL output
Series resonant crystal oscillator interface
Output frequency range: 25MHz to 700MHz
VCO range: 200MHz to 700MHz
Parallel interface for programming counter
and output dividers during power-up
Serial 3 wire interface
RMS Period jitter: 5.5ps (maximum)
Cycle-to-cycle jitter: 35ps (maximum)
3.3V supply voltage
0C to 70C ambient operating temperature
Lead-Free package fully RoHS compliant
Pin compatible with the MC12429
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
ICS84329
32-Lead LQFP
Y package
7mm x 7mm x 1.4mm
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
nc
N 1
N 0
M8
M7
M6
M5
M4
S_CLOCK
S_DATA
S_LOAD
V
CCA
V
CCA
nc
nc
XTAL_IN
nc
M3
M2
M1
M0
nP_LOAD
OE
XT
AL_OUT
V
EE
TEST
V
CC
V
CC
V
EE
nFOUT
FOUT
V
CC
B
LOCK
D
IAGRAM
ICS84329
28-Lead PLCC
V Package
11.6mm x 11.4mm x 4.1mm
Top View
25 24 23 22 21 20 19
5 6 7 8 9 10 11
26
27
28
1
2
3
4
18
17
16
15
14
13
12
S_CLOCK
S_DATA
S_LOAD
V
CCA
nc
nc
XTAL_IN
M3
M2
M1
M0
nP_LOAD
OE
XT
AL_OUT
V
EE
TEST
V
CC
V
EE
nFOUT
FOUT
V
CC
N 1
N 0
M8
M7
M6
M5
M4
OSC
XTAL_IN
XTAL_OUT
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
VCO
PLL
TEST
CONFIGURATION
INTERFACE
LOGIC
M
16
PHASE DETECTOR
FOUT
nFOUT
1
2
4
8
1
0
OE
84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
2
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
latched and the M divider remains loaded until the next LOW
transition on nP_LOAD or until a serial event occurs. The TEST
output is Mode 000 (shift register out) when operating in the
parallel input mode. The relationship between the VCO frequency,
the crystal frequency and the M divider is defined as follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are
defined as 200
M 511. The frequency out is defined as
follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider when S_LOAD tran-
sitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD.
If S_LOAD is held HIGH, data at the S_DATA input is passed
directly to the M divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and
test bits T2:T0. The internal registers T2:T0 determine the state
of the TEST output as follows:
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 6, NOTE 1.
The ICS84329 features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A series-resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector. With a 16MHz crys-
tal this provides a 1MHz reference frequency. The VCO of the
PLL operates over a range of 200MHz to 700MHz. The output
of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the
LVPECL output buffers. The divider provides a 50% output duty
cycle.
The programmable features of the ICS84329 support two input
modes to program the M divider and N output divider. The two
input operational modes are parallel and serial.
Figure 1 shows
the timing diagram for each mode. In parallel mode the nP_LOAD
input is LOW. The data on inputs M0 through M8 and N0 through
N1 is passed directly to the M divider and N output divider. On
the LOW-to-HIGH transition of the nP_LOAD input, the data is
N
fout =
fVCO
=
16
M
fxtal x
N
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
M, N
t
S
t
H
t
S
t
H
t
S
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
T2
T1
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
T2
T1
T0
TEST Output
0
0
0
Shift Register Out
0
0
1
High
0
1
0
PLL Reference Xtal 16
0
1
1
VCO M
(non 50% Duty M divider)
1
0
0
fOUT
LVCMOS Output Frequency < 200MHz
1
0
1
Low
1
1
0
S_CLOCK M
(non 50% Duty Cycle M divider)
1
1
1
fOUT 4
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
S_CLOCK N divider
fOUT
16
M
fVCO =
fxtal
x
84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
3
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
2. P
IN
C
HARACTERISTICS
T
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84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
4
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
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84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
5
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, T
A
= 0C
TO
70C
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,
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= V
CCA
= 3.3V5%, T
A
= 0C
TO
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ABLE
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= V
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= 3.3V5%, T
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2
/
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
For 28 Lead PLCC
37.8C/W (0 lfpm)
For 32 Lead LQFP
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
6
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
6. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
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,
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F
84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
7
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
P
ERIOD
J
ITTER
C
YCLE
-
TO
-C
YCLE
J
ITTER
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
S
ETUP
AND
H
OLD
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
contains 68.26% of all measurements
2
contains 95.4% of all measurements
3
contains 99.73% of all measurements
4
contains 99.99366% of all measurements
6
contains (100-1.973x10
-7
)% of all measurements
Histogram
-1.3V 0.165V
nFOUT
FOUT
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
FOUT
nFOUT
O
UTPUT
R
ISE
/F
ALL
T
IME
t
HOLD
t
HOLD
t
SET-UP
t
SET-UP
t
SET-UP
S_DATA
S_CLOCK
S_LOAD
M0:M8
N0:N1
nP_LOAD
V
EE
V
CC
,
V
CCA
84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
8
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84329 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
and V
CCA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
pin.
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
9
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
60
50
40
30
20
10
0
25
50
75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525
Output Frequency (MHz)
Time (pS)
F
IGURE
4B. C
YCLE
-
TO
-C
YCLE
J
ITTER
VS
. fOUT
(using a 16MHz XTAL)
F
IGURE
4A. RMS J
ITTER
VS
. fOUT
(using a 16MHz XTAL)
14
12
10
8
6
4
2
0
25
50
75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525
Output Frequency (MHz)
Time (pS)
84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
10
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
The ICS84329 features an internal oscillator that uses an external
quartz crystal as the source of its reference frequency. The
oscillator is a series resonant, multi-vibrator type design. This
design provides better stability and eliminates the need for large
on chip capacitors. Though a series resonant crystal is preferred,
a parallel resonant crystal can be used. A parallel resonant mode
crystal used in a series resonant circuit will exhibit a frequency
of oscillation a few hundred ppm lower than specified. A few
hundred ppm translates to KHz inaccuracy. In general computing
applications, this level of inaccuracy is irrelevant. If better ppm
accuracy is required, an external capacitor can be added to a
quartz crystal in series to XTAL_IN.
Figure 5A shows how to
interface with a crystal.
Figures 5A and 5B show various crystal parameters which are
recommended only as guidelines.
Figure 5A shows how to inter-
face a capacitor with a parallel resonant crystal.
Figure 5B shows
the capacitor value needed for the optimum ppm performance
over various series resonant crystal frequencies. For IA64/32
platforms which required a Raltron Parallel Resonant Quartz
crystal part #AS-16.66-18-SMD-T-M1, a 7pF series capacitor can
be used to better the ppm accuracy.
F
IGURE
5A. C
RYSTAL
I
NTERFACE
NOTE: For crystal frequencies higher than 17MHz,
a series tuning capacitor is required for proper operation.
XTAL_OUT
XTAL_IN
ICS84329
F
IGURE
5B. Recommended tuning capacitance for various series
resonant crystals.
C
RYSTAL
I
NPUT
AND
O
SCILLATOR
I
NTERFACE
10.000
14.318
12.000
24.000
20.000
16.000
0
5
10
15
20
25
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Series Resonant Crystal Frequency (MHz)
Ser
i
es
Capac
itor
(
pf)
84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
11
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
The schematic of the ICS84329 layout example used in this
layout guideline is shown in
Figure 6A. The ICS84329 recommended
PCB board layout for this example is shown in
Figure 6B. This
layout example is used as a general guideline. The layout in the
L
AYOUT
G
UIDELINE
F
IGURE
6A. S
CHEMATIC
OF
R
ECOMMENDED
L
AYOUT
actual system will depend on the selected component types, the
density of the components, the density of the traces, and the stack
up of the P.C. board.
OE
M4
OE
M7
nPLO
A
D
nPLoad
RD1
1K
M5
N0
VCC
M6
C2
0.1u
VCC
M1
C4
22p
RD0
1K
Zo = 50 Ohm
U1
84329AV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
27
26
25
24
23
22
21
28
VCCA
nc
nc
XTALIN
XT
AL
OU
T
OE
nP_LO
AD
M0
M1
M2
M3
M4
M5
M6
M7
M8
N0
N1
VE
E
TE
S
T
S_DATA
S_CLOCK
VC
C
FO
U
T
nF
O
U
T
VE
E
VC
C
S_LOAD
RU8
1K
M7
Zo = 50 Ohm
Fo ut = 2 00 M Hz
R3
50
C16
10u
V CC=3 .3 V
RU9
SP
C3
22p
RD7
SP
R7
10
RU1
SP
M [8:0]= 11 0 01 0 00 0 (4 00 )
N1
RU11
SP
RU10
1K
S P = S p ace (i .e . n o t i ntsta l l e d )
VC
C
M0
RD9
1K
X1
16MHz,18pF
RD6
1K
RU7
1K
M0
VCCA
M2
N2
M8
RD8
SP
C11
0.01u
C1
0.1uF
M3
M8
RU12
1K
R1
50
R2
50
N[1 :0 ] =0 1 (Di vi d e by 2 )
M1
RU0
SP
RD10
SP
N1
RD12
SP
84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
12
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
F
IGURE
6B. PCB B
OARD
L
AYOUT
FOR
ICS84329
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C1, C2 and C3, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
CCA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have the
same length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
4 (XTAL_IN) and 5 (XTAL_IN). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
C16
X1
C2
VCC
PIN 2
C11
C1
GND
VIA
50 Ohm
Traces
R7
VCCA
Signals
Traces
U1
PIN 1
VCCA
84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
13
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8C/W
31.1C/W
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
8A. T
HERMAL
R
ESISTANCE
JA
FOR
28-
PIN
PLCC, F
ORCED
C
ONVECTION
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
8B. T
HERMAL
R
ESISTANCE
JA
FOR
32-
PIN
LQFP, F
ORCED
C
ONVECTION
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84329.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84329 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 140mA = 485mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 1 * 30.2mW = 30.2mW
Total Power
_MAX
(3.465V, with all outputs switching) = 485mW + 30.2mW = 515.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1C/W per Table 8A below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.515W * 31.1C/W = 86C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
14
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in the
Figure 7.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
1.0V
(V
CC_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CC_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
7. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
15
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8C/W
31.1C/W
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS84329 is: 4408
T
ABLE
9A.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
28 L
EAD
PLCC
JA
by Velocity (Linear Feet per Minute)
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
9B.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP
84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
16
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- V S
UFFIX
FOR
28 L
EAD
PLCC
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
M
U
M
I
N
I
M
M
U
M
I
X
A
M
N
8
2
A
9
1
.
4
7
5
.
4
1
A
9
2
.
2
5
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Reference Document: JEDEC Publication 95, MS-018
84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
17
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
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LVPECL F
REQUENCY
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10B. P
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Reference Document: JEDEC Publication 95, MS-026
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84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
18
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
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D
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LVPECL F
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While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
84329AV
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 15, 2004
19
Integrated
Circuit
Systems, Inc.
ICS84329
700MH
Z
, L
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J
ITTER
, C
RYSTAL
-
TO
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D
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LVPECL F
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