ChipFind - документация

Электронный компонент: ICS84329B

Скачать:  PDF   ZIP

Document Outline

84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
1
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS84329B is a general purpose, single
output high frequency synthesizer and a
member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. The
VCO operates at a frequency range of 250MHz
to 700MHz. The VCO frequency is programmed in steps equal
to the value of the crystal frequency divided by 16. The VCO
and output frequency can be programmed using the serial or
parallel interfaces to the configuration logic. The output can
be configured to divide the VCO frequency by 1, 2, 4, and 8.
Output frequency steps as small as 125kHz to 1MHz
can be achieved using a 16MHz crystal depending on the
output dividers.
F
EATURES
Fully integrated PLL, no external loop filter requirements
One differential 3.3V LVPECL output
Parallel resonant crystal oscillator interface
Output frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
Parallel interface for programming counter
and output dividers during power-up
Serial 3 wire interface
RMS Period jitter: 5.5ps (maximum)
Cycle-to-cycle jitter: 35ps (maximuml)
3.3V supply voltage
0C to 70C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
ICS84329B
32-Lead LQFP
Y package
7mm x 7mm x 1.4mm
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
nc
N 1
N 0
M8
M7
M6
M5
M4
S_CLOCK
S_DATA
S_LOAD
V
CCA
V
CCA
nc
nc
XTAL_IN
nc
M3
M2
M1
M0
nP_LOAD
OE
XT
AL_OUT
V
EE
TEST
V
CC
V
CC
V
EE
nFOUT
FOUT
V
CC
B
LOCK
D
IAGRAM
ICS84329B
28-Lead PLCC
V Package
11.6mm x 11.4mm x 4.1mm
Top View
25 24 23 22 21 20 19
5 6 7 8 9 10 11
26
27
28
1
2
3
4
18
17
16
15
14
13
12
S_CLOCK
S_DATA
S_LOAD
V
CCA
nc
nc
XTAL_IN
M3
M2
M1
M0
nP_LOAD
OE
XT
AL_OUT
V
EE
TEST
V
CC
V
EE
nFOUT
FOUT
V
CC
N 1
N 0
M8
M7
M6
M5
M4
OSC
XTAL_IN
XTAL_OUT
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
VCO
PLL
TEST
CONFIGURATION
INTERFACE
LOGIC
M
16
PHASE DETECTOR
FOUT
nFOUT
1
2
4
8
1
0
OE
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
2
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a
serial event occurs. The TEST output is Mode 000 (shift reg-
ister out) when operating in the parallel input mode. The rela-
tionship between the VCO frequency, the crystal frequency
and the M divider is defined as follows:
The M value and the required values of M0 through M8
are shown in Table 3B, Programmable VCO Frequency
Function Table. Valid M values for which the PLL will
achieve lock are defined as 250
M 511. The frequency
out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider when S_LOAD tran-
sitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD.
If S_LOAD is held HIGH, data at the S_DATA input is passed
directly to the M divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and
test bits T2:T0. The internal registers T2:T0 determine the state
of the TEST output as follows:
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 6, NOTE 1.
The ICS84329B features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A series-resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector. With a 16MHz crys-
tal this provides a 1MHz reference frequency. The VCO of the
PLL operates over a range of 250MHz to 700MHz. The output
of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS84329B support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial.
Fig-
ure 1
shows the timing diagram for each mode. In parallel mode
the nP_LOAD input is LOW. The data on inputs M0 through
M8 and N0 through N1 is passed directly to the M divider and
N
fout =
fVCO
=
16
M
fxtal x
N
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
t
S
t
H
t
S
t
H
t
S
M, N
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
T2
T1
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
S_LOAD
16
M
fVCO =
fxtal
x
T2
T1
T0
TEST Output
0
0
0
Shift Register Out
0
0
1
High
0
1
0
PLL Reference Xtal 16
0
1
1
VCO M
(non 50% Duty M divider)
1
0
0
fOUT
LVCMOS Output Frequency < 200MHz
1
0
1
Low
1
1
0
S_CLOCK M
(non 50% Duty Cycle M divider)
1
1
1
fOUT 4
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
S_CLOCK N divider
fOUT
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
3
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
1. P
IN
D
ESCRIPTIONS
e
m
a
N
e
p
y
T
n
o
i
t
p
i
r
c
s
e
D
V
A
C
C
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
g
o
l
a
n
A
,
N
I
_
L
A
T
X
T
U
O
_
L
A
T
X
t
u
p
n
I
.
t
u
p
t
u
o
e
h
t
s
i
T
U
O
_
L
A
T
X
.
t
u
p
n
i
e
h
t
s
i
N
I
_
L
A
T
X
.
e
c
a
f
r
e
t
n
i
r
o
t
a
ll
i
c
s
o
l
a
t
s
y
r
C
E
O
t
u
p
n
I
p
u
ll
u
P
.
)
t
l
u
a
f
e
d
(
d
e
l
b
a
n
e
e
r
a
s
t
u
p
t
u
o
e
h
t
,
H
G
I
H
c
i
g
o
l
n
e
h
W
.
e
l
b
a
n
e
t
u
p
t
u
O
:
w
o
l
l
a
i
t
n
e
r
e
f
f
i
d
e
v
i
r
d
d
n
a
d
e
l
b
a
s
i
d
e
r
a
s
t
u
p
t
u
o
e
h
t
,
W
O
L
c
i
g
o
l
n
e
h
W
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
H
G
I
H
=
T
U
O
F
n
,
W
O
L
=
T
U
O
F
D
A
O
L
_
P
n
t
u
p
n
I
p
u
ll
u
P
o
t
n
i
d
e
d
a
o
l
s
i
0
M
:
8
M
t
a
t
n
e
s
e
r
p
a
t
a
d
n
e
h
w
s
e
n
i
m
r
e
t
e
D
.
t
u
p
n
i
d
a
o
l
l
e
ll
a
r
a
P
.
e
u
l
a
v
e
d
i
v
i
d
t
u
p
t
u
o
N
e
h
t
s
t
e
s
0
N
:
1
N
t
a
t
n
e
s
e
r
p
a
t
a
d
n
e
h
w
d
n
a
,
r
e
d
i
v
i
d
M
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
,
3
M
,
2
M
,
1
M
,
0
M
8
M
,
7
M
,
6
M
,
5
M
,
4
M
t
u
p
n
I
p
u
ll
u
P
.
t
u
p
n
i
D
A
O
L
_
P
n
f
o
n
o
i
t
s
i
s
n
a
r
t
H
G
I
H
-
o
t
-
W
O
L
n
o
d
e
h
c
t
a
l
a
t
a
D
.
s
t
u
p
n
i
r
e
d
i
v
i
d
M
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
1
N
,
0
N
t
u
p
n
I
p
u
ll
u
P
.
e
l
b
a
T
n
o
i
t
c
n
u
F
C
3
e
l
b
a
T
n
i
d
e
n
i
f
e
d
s
a
e
u
l
a
v
r
e
d
i
v
i
d
t
u
p
t
u
o
N
s
e
n
i
m
r
e
t
e
D
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
V
E
E
r
e
w
o
P
.
s
n
i
p
y
l
p
p
u
s
e
v
i
t
a
g
e
N
T
S
E
T
t
u
p
t
u
O
.
n
o
i
t
a
r
e
p
o
f
o
e
d
o
m
l
a
i
r
e
s
e
h
t
n
i
d
e
s
u
s
i
h
c
i
h
w
t
u
p
t
u
o
t
s
e
T
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
V
C
C
r
e
w
o
P
.
s
n
i
p
y
l
p
p
u
s
e
r
o
C
T
U
O
F
,
T
U
O
F
n
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
C
E
P
V
L
V
3
.
3
.
r
e
z
i
s
e
h
t
n
y
s
e
h
t
r
o
f
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
K
C
O
L
C
_
S
t
u
p
n
I
n
w
o
d
ll
u
P
e
h
t
n
o
r
e
t
s
i
g
e
r
t
f
i
h
s
e
h
t
o
t
n
i
t
u
p
n
i
A
T
A
D
_
S
t
a
t
n
e
s
e
r
p
a
t
a
d
l
a
i
r
e
s
e
h
t
s
k
c
o
l
C
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
K
C
O
L
C
_
S
f
o
e
g
d
e
g
n
i
s
i
r
A
T
A
D
_
S
t
u
p
n
I
n
w
o
d
ll
u
P
.
K
C
O
L
C
_
S
f
o
e
g
d
e
g
n
i
s
i
r
e
h
t
n
o
d
e
l
p
m
a
s
a
t
a
D
.
t
u
p
n
i
l
a
i
r
e
s
r
e
t
s
i
g
e
r
t
f
i
h
S
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
D
A
O
L
_
S
t
u
p
n
I
n
w
o
d
ll
u
P
.
r
e
d
i
v
i
d
M
e
h
t
o
t
n
i
r
e
t
s
i
g
e
r
t
f
i
h
s
m
o
r
f
a
t
a
d
f
o
n
o
i
t
i
s
n
a
r
t
s
l
o
r
t
n
o
C
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
:
E
T
O
N
p
u
ll
u
P
d
n
a
n
w
o
d
ll
u
P
.
s
e
u
l
a
v
l
a
c
i
p
y
t
r
o
f
,
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
n
i
P
,
2
e
l
b
a
T
e
e
S
.
s
r
o
t
s
i
s
e
r
t
u
p
n
i
l
a
n
r
e
t
n
i
o
t
r
e
f
e
r
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
C
N
I
e
c
n
a
t
i
c
a
p
a
C
t
u
p
n
I
4
F
p
R
P
U
L
L
U
P
r
o
t
s
i
s
e
R
p
u
ll
u
P
t
u
p
n
I
1
5
k
R
N
W
O
D
L
L
U
P
r
o
t
s
i
s
e
R
n
w
o
d
ll
u
P
t
u
p
n
I
1
5
k
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
4
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
y
c
n
e
u
q
e
r
F
O
C
V
)
z
H
M
(
e
d
i
v
i
D
M
6
5
2
8
2
1
4
6
2
3
6
1
8
4
2
1
8
M
7
M
6
M
5
M
4
M
3
M
2
M
1
M
0
M
0
5
2
0
5
2
0
1
1
1
1
1
0
1
0
1
5
2
1
5
2
0
1
1
1
1
1
0
1
1
2
5
2
2
5
2
0
1
1
1
1
1
1
0
0
3
5
2
3
5
2
0
1
1
1
1
1
1
0
1
9
0
5
9
0
5
1
1
1
1
1
1
1
0
1
0
1
5
0
1
5
1
1
1
1
1
1
1
1
0
1
1
5
1
1
5
1
1
1
1
1
1
1
1
1
.
z
H
M
6
1
f
o
y
c
n
e
u
q
e
r
f
l
a
t
s
y
r
c
a
o
t
d
n
o
p
s
e
r
r
o
c
s
e
i
c
n
e
u
q
e
r
f
g
n
i
t
l
u
s
e
r
e
h
t
d
n
a
s
e
u
l
a
v
e
d
i
v
i
d
M
e
s
e
h
T
:
1
E
T
O
N
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
s
t
u
p
n
I
s
n
o
i
t
i
d
n
o
C
D
A
O
L
_
P
n
M
N
D
A
O
L
_
S
K
C
O
L
C
_
S
A
T
A
D
_
S
X
X
X
X
X
X
.
H
G
I
H
t
e
s
ll
a
e
r
a
s
t
i
b
N
d
n
a
M
.
t
e
s
e
R
L
a
t
a
D
a
t
a
D
X
X
X
d
n
a
r
e
d
i
v
i
d
M
o
t
y
l
t
c
e
r
i
d
d
e
s
s
a
p
s
t
u
p
n
i
N
d
n
a
M
n
o
a
t
a
D
.
0
0
0
e
d
o
m
T
S
E
T
.
r
e
d
i
v
i
d
t
u
p
t
u
o
N
a
t
a
D
a
t
a
D
L
X
X
d
e
d
a
o
l
s
n
i
a
m
e
r
d
n
a
s
r
e
t
s
i
g
e
r
t
u
p
n
i
o
t
n
i
d
e
h
c
t
a
l
s
i
a
t
a
D
.
s
r
u
c
c
o
t
n
e
v
e
l
a
i
r
e
s
a
li
t
n
u
r
o
n
o
i
t
i
s
n
a
r
t
W
O
L
t
x
e
n
li
t
n
u
H
X
X
L
a
t
a
D
n
o
a
t
a
d
h
t
i
w
d
e
d
a
o
l
s
i
r
e
t
s
i
g
e
r
t
f
i
h
S
.
e
d
o
m
t
u
p
n
i
l
a
i
r
e
S
.
K
C
O
L
C
_
S
f
o
e
g
d
e
g
n
i
s
i
r
h
c
a
e
n
o
A
T
A
D
_
S
H
X
X
L
a
t
a
D
r
e
d
i
v
i
d
M
e
h
t
o
t
d
e
s
s
a
p
e
r
a
r
e
t
s
i
g
e
r
t
f
i
h
s
e
h
t
f
o
s
t
n
e
t
n
o
C
.
r
e
d
i
v
i
d
t
u
p
t
u
o
N
d
n
a
H
X
X
L
a
t
a
D
.
d
e
h
c
t
a
l
e
r
a
s
e
u
l
a
v
e
d
i
v
i
d
t
u
p
t
u
o
N
d
n
a
e
d
i
v
i
d
M
H
X
X
L
X
X
.
s
r
e
t
s
i
g
e
r
t
f
i
h
s
t
c
e
f
f
a
t
o
n
o
d
t
u
p
n
i
l
a
i
r
e
s
r
o
l
e
ll
a
r
a
P
W
O
L
=
L
:
E
T
O
N
H
G
I
H
=
H
e
r
a
c
t
'
n
o
D
=
X
n
o
i
t
i
s
n
a
r
t
e
g
d
e
g
n
i
s
i
R
=
n
o
i
t
i
s
n
a
r
t
e
g
d
e
g
n
il
l
a
F
=
s
t
u
p
n
I
e
u
l
a
V
r
e
d
i
v
i
D
N
)
z
H
M
(
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
1
N
0
N
m
u
m
i
n
i
M
m
u
m
i
x
a
M
0
0
1
0
5
2
0
0
7
0
1
2
5
2
1
0
5
3
1
0
4
5
.
2
6
5
7
1
1
1
8
5
2
.
1
3
5
.
7
8
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
5
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
O
1
E
T
O
N
;
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
V
C
C
4
.
1
-
V
C
C
9
.
0
-
V
V
L
O
1
E
T
O
N
;
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
V
C
C
0
.
2
-
V
C
C
7
.
1
-
V
V
G
N
I
W
S
g
n
i
w
S
e
g
a
t
l
o
V
t
u
p
t
u
O
k
a
e
P
-
o
t
-
k
a
e
P
6
.
0
0
.
1
V
0
5
h
t
i
w
d
e
t
a
n
i
m
r
e
t
s
t
u
p
t
u
O
:
1
E
T
O
N
V
o
t
C
C
.
V
2
-
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
C
C
e
g
a
t
l
o
V
y
l
p
p
u
S
e
r
o
C
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
A
C
C
e
g
a
t
l
o
V
y
l
p
p
u
S
g
o
l
a
n
A
5
3
1
.
3
3
.
3
5
6
4
.
3
V
I
C
C
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
5
2
1
A
m
I
A
C
C
t
n
e
r
r
u
C
y
l
p
p
u
S
g
o
l
a
n
A
5
1
A
m
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
I
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
2
V
C
C
3
.
0
+
V
V
L
I
e
g
a
t
l
o
V
w
o
L
t
u
p
n
I
3
.
0
-
8
.
0
V
I
H
I
t
n
e
r
r
u
C
h
g
i
H
t
u
p
n
I
,
1
N
,
0
N
,
8
M
-
0
M
D
A
O
L
_
P
n
,
E
O
V
C
C
V
=
N
I
V
5
6
4
.
3
=
5
A
,
D
A
O
L
_
S
K
C
O
L
C
_
S
,
A
T
A
D
_
S
V
C
C
V
=
N
I
V
5
6
4
.
3
=
0
5
1
A
I
L
I
t
n
e
r
r
u
C
w
o
L
t
u
p
n
I
,
1
N
,
0
N
,
8
M
-
0
M
D
A
O
L
_
P
n
,
E
O
V
C
C
V
,
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
,
D
A
O
L
_
S
K
C
O
L
C
_
S
,
A
T
A
D
_
S
V
C
C
V
,
V
5
6
4
.
3
=
N
I
V
0
=
5
-
A
V
H
O
1
E
T
O
N
;
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
6
.
2
V
V
L
O
1
E
T
O
N
;
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
5
.
0
V
0
5
h
t
i
w
d
e
t
a
n
i
m
r
e
t
s
t
u
p
t
u
O
:
1
E
T
O
N
V
o
t
C
C
.
t
i
u
c
r
i
C
t
s
e
T
d
a
o
L
t
u
p
t
u
O
V
3
.
3
,
n
o
i
t
a
m
r
o
f
n
I
t
n
e
m
e
r
u
s
a
e
M
r
e
t
e
m
a
r
a
P
e
e
S
.
2
/
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
37.8C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
6
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
6. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
N
I
y
c
n
e
u
q
e
r
F
t
u
p
n
I
1
E
T
O
N
;
L
A
T
X
0
1
5
2
z
H
M
K
C
O
L
C
_
S
0
5
z
H
M
y
c
n
e
u
q
e
r
f
O
C
V
m
u
m
i
x
a
m
r
o
m
u
m
i
n
i
m
e
h
t
e
v
e
i
h
c
a
o
t
t
e
s
e
b
t
s
u
m
e
u
l
a
v
M
e
h
t
e
g
n
a
r
y
c
n
e
u
q
e
r
f
l
a
t
s
y
r
c
e
h
t
r
o
F
:
1
E
T
O
N
0
0
4
e
r
a
M
f
o
s
e
u
l
a
v
d
il
a
v
z
H
M
0
1
f
o
y
c
n
e
u
q
e
r
f
m
u
m
i
n
i
m
e
h
t
g
n
i
s
U
.
z
H
M
0
0
7
r
o
z
H
M
0
5
2
f
o
e
g
n
a
r
M
.
1
1
5
0
6
1
e
r
a
M
f
o
s
e
u
l
a
v
d
il
a
v
z
H
M
5
2
f
o
y
c
n
e
u
q
e
r
f
m
u
m
i
x
a
m
e
h
t
g
n
i
s
U
M
.
8
4
4
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
n
o
i
t
a
ll
i
c
s
O
f
o
e
d
o
M
l
a
t
n
e
m
a
d
n
u
F
y
c
n
e
u
q
e
r
F
0
1
5
2
z
H
M
)
R
S
E
(
e
c
n
a
t
s
i
s
e
R
s
e
i
r
e
S
t
n
e
l
a
v
i
u
q
E
0
5
e
c
n
a
t
i
c
a
p
a
C
t
n
u
h
S
7
F
p
l
e
v
e
L
e
v
i
r
D
1
W
m
T
ABLE
7. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
F
T
U
O
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
0
0
7
z
H
M
t
)
r
e
p
(
t
ij
2
,
1
E
T
O
N
;
S
M
R
,
r
e
t
t
i
J
d
o
i
r
e
P
T
U
O
f
z
H
M
5
6
5
.
5
s
p
z
H
M
5
6
<
T
U
O
f
2
1
s
p
t
)
c
c
(
t
ij
2
,
1
E
T
O
N
;
r
e
t
t
i
J
e
l
c
y
C
-
o
t
-
e
l
c
y
C
T
U
O
f
z
H
M
0
5
5
3
s
p
T
U
O
f
<
z
H
M
0
5
0
5
s
p
t
R
t
/
F
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
0
3
0
0
8
s
p
t
S
e
m
i
T
p
u
t
e
S
5
s
n
t
H
e
m
i
T
d
l
o
H
5
s
n
t
L
e
m
i
T
k
c
o
L
L
L
P
0
1
s
m
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
5
4
0
5
5
5
%
.
n
o
i
t
c
e
s
n
o
i
t
a
m
r
o
f
n
I
t
n
e
m
e
r
u
s
a
e
M
r
e
t
e
m
a
r
a
P
e
e
S
.
L
A
T
X
z
H
M
6
1
a
g
n
i
s
u
d
e
z
i
r
e
t
c
a
r
a
h
C
5
6
d
r
a
d
n
a
t
S
C
E
D
E
J
h
t
i
w
e
c
n
a
d
r
o
c
c
a
n
i
d
e
n
i
f
e
d
s
i
r
e
t
e
m
a
r
a
p
s
i
h
T
:
1
E
T
O
N
.
n
o
i
t
c
e
s
s
n
o
i
t
a
c
il
p
p
A
e
e
S
:
2
E
T
O
N
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
7
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
P
ERIOD
J
ITTER
C
YCLE
-
TO
-C
YCLE
J
ITTER
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
S
ETUP
AND
H
OLD
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
contains 68.26% of all measurements
2
contains 95.4% of all measurements
3
contains 99.73% of all measurements
4
contains 99.99366% of all measurements
6
contains (100-1.973x10
-7
)% of all measurements
Histogram
-1.3V 0.165V
nFOUT
FOUT
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
FOUT
nFOUT
O
UTPUT
R
ISE
/F
ALL
T
IME
t
HOLD
t
HOLD
t
SET-UP
t
SET-UP
t
SET-UP
S_DATA
S_CLOCK
S_LOAD
M0:M8
N0:N1
nP_LOAD
V
CC
,
V
CCA
V
EE
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
8
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84329B provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
and V
CCA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
pin. The 10
resistor can also be replaced by a ferrite bead.
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS84329B has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown
in
Figure 3
below were determined using a 25MHz, 18pF
Figure 3. C
RYSTAL
I
NPU
t I
NTERFACE
parallel resonant crystal and were chosen to minimize the
ppm error. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
ICS84332
XTAL_IN
XTAL_OUT
X1
18pF Parallel Cry stal
C2
22p
C1
22p
I
NPUTS
:
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
P
INS
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
9
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
60
50
40
30
20
10
0
25
50
75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525
Output Frequency (MHz)
Time (pS)
F
IGURE
4B. C
YCLE
-
TO
-C
YCLE
J
ITTER
VS
. fOUT
(using a 16MHz XTAL)
F
IGURE
4A. RMS J
ITTER
VS
. fOUT
(using a 16MHz XTAL)
14
12
10
8
6
4
2
0
25
50
75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525
Output Frequency (MHz)
Time (pS)
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
10
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
The schematic of the ICS84329B layout example used in this
layout guideline is shown in
Figure 5A.
The ICS84329B recom-
mended PCB board layout for this example is shown in
Figure
5B.
This layout example is used as a general guideline. The
L
AYOUT
G
UIDELINE
F
IGURE
5A. S
CHEMATIC
OF
R
ECOMMENDED
L
AYOUT
FOR
28 L
EAD
PLCC
layout in the actual system will depend on the selected compo-
nent types, the density of the components, the density of the
traces, and the stack up of the P.C. board.
OE
RU10
1K
R7
10
R2
50
M0
RD6
1K
RD9
1K
N1
N2
M3
Zo = 50 Ohm
RD8
SP
M7
VCC
RD0
1K
RD12
SP
M2
C4
22p
nP
LOA
D
RU9
SP
nPL
oad
V CC=3 .3V
N1
Zo = 50 Ohm
M [8 :0]= 11 00 1 00 0 0 (40 0 )
C3
22p
C11
0.01u
S P = S p ace (i .e. n ot i ntstal l e d)
M4
RU7
1K
M8
R1
50
N[1 :0 ] =01 (Di vid e by 2)
R3
50
VCCA
RU11
SP
M1
VC
C
C2
0.1u
RU8
1K
M8
N0
RD7
SP
RU0
SP
M0
RD10
SP
C16
10u
M5
U1
84329BV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
27
26
25
24
23
22
21
28
VCCA
nc
nc
XTALIN
XT
ALO
U
T
OE
nP
_LO
AD
M0
M1
M2
M3
M4
M5
M6
M7
M8
N0
N1
VEE
TE
S
T
S_DATA
S_CLOCK
VC
C
FO
U
T
nF
O
U
T
VEE
VC
C
S_LOAD
M1
RD1
1K
RU1
SP
Fou t = 2 00 M Hz
M7
OE
C1
0.1uF
RU12
1K
VCC
M6
X1
16MHz,18pF
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
11
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
F
IGURE
5B. PCB B
OARD
L
AYOUT
FOR
ICS84329B 28 L
EAD
PLCC
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C1, C2 and C3, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
CCA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have the
same length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
4 (XTAL_IN) and 5 (XTAL_OUT). The trace length between the
X1 and U1 should be kept to a minimum to avoid unwanted para-
sitic inductance and capacitance. Other signal traces should not
be routed near the crystal traces.
C3
C1
X1
VCC
C16
C4
PIN 1
C2
Signals
Traces
C11
GND
R7
U1
PIN 2
VCCA
VIA
VCCA
50 Ohm
Traces
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
12
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
F
IGURE
6B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
6A. LVPECL O
UTPUT
T
ERMINATION
designed to drive 50
transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minmize signal distortion.
Figures 6A and
6B
show two different layouts which are recommended only
as guidelines.Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
13
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER


JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8C/W
31.1C/W
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
8A. T
HERMAL
R
ESISTANCE


JA
FOR
28-
PIN
PLCC, F
ORCED
C
ONVECTION


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
8B. T
HERMAL
R
ESISTANCE


JA
FOR
32-
PIN
LQFP, F
ORCED
C
ONVECTION
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84329B.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84329B is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 140mA = 485mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power
_MAX
(3.465V, with all outputs switching) = 485mW + 30mW = 515mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1C/W per Table 8A below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.515W * 31.1C/W = 86C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
14
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in the
Figure 7.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
0.9V
(V
CC_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CC_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
7. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
15
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8C/W
31.1C/W
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS84329B is: 4408
Pin compatible with the MC12429
T
ABLE
9A.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
28 L
EAD
PLCC


JA
by Velocity (Linear Feet per Minute)


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
9B.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
16
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- V S
UFFIX
FOR
28 L
EAD
PLCC
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
M
U
M
I
N
I
M
M
U
M
I
X
A
M
N
8
2
A
9
1
.
4
7
5
.
4
1
A
9
2
.
2
5
0
.
3
2
A
7
5
.
1
1
1
.
2
b
3
3
.
0
3
5
.
0
c
9
1
.
0
2
3
.
0
D
2
3
.
2
1
7
5
.
2
1
1
D
3
4
.
1
1
8
5
.
1
1
2
D
5
8
.
4
6
5
.
5
E
2
3
.
2
1
7
5
.
2
1
1
E
3
4
.
1
1
8
5
.
1
1
2
E
5
8
.
4
6
5
.
5
T
ABLE
10A. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-018
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
17
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
32 L
EAD
LQFP
T
ABLE
10B. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
3
A
-
-
-
-
0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
9
0
.
0
-
-
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
.
f
e
R
0
6
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
.
f
e
R
0
6
.
5
e
C
I
S
A
B
0
8
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0




0
-
-
7
c
c
c
-
-
-
-
0
1
.
0
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
18
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
11. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
r
e
b
m
u
N
r
e
d
r
O
/
t
r
a
P
g
n
i
k
r
a
M
e
g
a
k
c
a
P
g
n
i
g
a
k
c
a
P
g
n
i
p
p
i
h
S
e
r
u
t
a
r
e
p
m
e
T
V
B
9
2
3
4
8
S
C
I
V
B
9
2
3
4
8
S
C
I
C
C
L
P
d
a
e
L
8
2
e
b
u
T
C
0
7
o
t
C
0
T
V
B
9
2
3
4
8
S
C
I
V
B
9
2
3
4
8
S
C
I
C
C
L
P
d
a
e
L
8
2
l
e
e
R
&
e
p
a
T
0
0
5
C
0
7
o
t
C
0
F
L
V
B
9
2
3
4
8
S
C
I
F
L
V
B
9
2
3
4
8
S
C
I
C
C
L
P
"
e
e
r
F
-
d
a
e
L
"
d
a
e
L
8
2
e
b
u
T
C
0
7
o
t
C
0
T
F
L
V
B
9
2
3
4
8
S
C
I
F
L
V
B
9
2
3
4
8
S
C
I
C
C
L
P
"
e
e
r
F
-
d
a
e
L
"
d
a
e
L
8
2
l
e
e
R
&
e
p
a
T
0
0
5
C
0
7
o
t
C
0
Y
B
9
2
3
4
8
S
C
I
Y
B
9
2
3
4
8
S
C
I
P
F
Q
L
d
a
e
L
2
3
y
a
r
T
C
0
7
o
t
C
0
T
Y
B
9
2
3
4
8
S
C
I
Y
B
9
2
3
4
8
S
C
I
P
F
Q
L
d
a
e
L
2
3
l
e
e
R
&
e
p
a
T
0
0
0
1
C
0
7
o
t
C
0
F
L
Y
B
9
2
3
4
8
S
C
I
F
L
Y
B
9
2
3
4
8
S
C
I
P
F
Q
L
"
e
e
r
F
-
d
a
e
L
"
d
a
e
L
2
3
y
a
r
T
C
0
7
o
t
C
0
T
F
L
Y
B
9
2
3
4
8
S
C
I
F
L
Y
B
9
2
3
4
8
S
C
I
P
F
Q
L
"
e
e
r
F
-
d
a
e
L
"
d
a
e
L
2
3
l
e
e
R
&
e
p
a
T
0
0
0
1
C
0
7
o
t
C
0
.
t
n
a
il
p
m
o
c
S
H
o
R
e
r
a
d
n
a
n
o
i
t
a
r
u
g
i
f
n
o
c
e
e
r
F
-
b
P
e
h
t
e
r
a
r
e
b
m
u
n
t
r
a
p
e
h
t
o
t
x
i
f
f
u
s
"
F
L
"
n
a
h
t
i
w
d
e
r
e
d
r
o
e
r
a
r
a
h
t
s
t
r
a
P
:
E
T
O
N
84329BV
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
19
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
E
E
H
S
Y
R
O
T
S
I
H
N
O
I
S
I
V
E
R
v
e
R
e
l
b
a
T
e
g
a
P
e
g
n
a
h
C
f
o
n
o
i
t
p
i
r
c
s
e
D
e
t
a
D
A
1
.
t
e
ll
u
b
l
a
t
s
y
r
c
o
t
"
t
n
a
n
o
s
e
r
l
e
ll
a
r
a
P
"
d
e
d
d
a
-
n
o
i
t
c
e
S
s
e
r
u
t
a
e
F
4
0
/
5
1
/
2
1
B
5
T
1
1
T
1
2
6
7
1
o
t
z
H
M
5
2
m
o
r
f
e
g
n
a
r
y
c
n
e
u
q
e
r
f
t
u
p
t
u
O
d
e
t
c
e
r
r
o
c
-
n
o
i
t
c
e
S
s
e
r
u
t
a
e
F
.
t
e
ll
u
b
e
e
r
F
-
d
a
e
L
d
e
d
d
A
.
z
H
M
5
2
.
1
3
.
s
n
o
i
t
a
r
e
p
O
d
a
o
L
l
a
i
r
e
S
&
l
e
ll
a
r
a
P
d
e
t
a
d
p
U
.
l
e
v
e
L
e
v
i
r
D
d
e
d
d
a
-
e
l
b
a
T
l
a
t
s
y
r
C
.
e
t
o
n
d
n
a
s
r
e
b
m
u
n
t
r
a
p
e
e
r
F
-
d
a
e
L
d
e
d
d
a
-
e
l
b
a
T
n
o
i
t
a
m
r
o
f
n
I
g
n
i
r
e
d
r
O
5
0
/
0
1
/
6
B
1
1
T
8
8
8
1
.
e
c
n
e
t
n
e
s
d
a
e
b
e
t
i
r
r
e
f
d
e
d
d
a
-
s
e
u
q
i
n
h
c
e
T
g
n
i
r
e
t
li
F
y
l
p
p
u
S
r
e
w
o
P
d
e
d
d
A
.
s
n
i
P
t
u
p
t
u
O
d
n
a
t
u
p
n
I
d
e
s
u
n
U
r
o
f
s
n
o
i
t
a
d
n
e
m
m
o
c
e
R
.
g
n
i
k
r
a
m
e
e
r
F
-
d
a
e
L
d
e
d
d
a
-
e
l
b
a
T
n
o
i
t
a
m
r
o
f
n
I
g
n
i
r
e
d
r
O
6
0
/
8
1
/
1