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Электронный компонент: ICS8432BYI-51

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8432BYI-51
www.icst.com/products/hiperclocks.html
REV. A MAY 28, 2003
1
Integrated
Circuit
Systems, Inc.
ICS8432I-51
700MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS8432I-51 is a general purpose, dual output
Crystal-to-3.3V Differential LVPECL High Fre-
quency Synthesizer and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The ICS8432I-51 has a select-
able TEST_CLK or crystal input. The VCO operates at a
frequency range of 250MHz to 700MHz. The VCO frequency
is programmed in steps equal to the value of the input refer-
ence or crystal frequency. The VCO and output frequency
can be programmed using the serial or parallel interface to
the configuration logic. The low phase noise characteristics
of the ICS8432I-51 make it an ideal clock source for Gigabit
Ethernet, Fibre Channel 1 and 2, and Infiniband applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Dual differential 3.3V LVPECL outputs
Selectable crystal oscillator interface or
LVCMOS/LVTTL TEST_CLK
Output frequency range: 31.25MHz to 700MHz
Crystal input frequency range: 12MHz to 25MHz
VCO range: 250MHz to 700MHz
Parallel or serial interface for programming counter
and output dividers
RMS period jitter: 3.5ps (maximum)
Cycle-to-cycle jitter: 25ps (maximum)
3.3V supply voltage
-40C to 85C ambient operating temperature
Replaces the ICS8432I-01
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL2
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N 0
N 1
nc
V
EE
V
EE
nFOUT0
FOUT0
V
CCO
nFOUT1
FOUT1
V
CC
TEST
X
T
AL1
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8432I-51
HiPerClockSTM
,&6
OSC
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL1
XTAL2
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
VCO
PLL
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
CONFIGURATION
INTERFACE
LOGIC
M
0
1
0
1
PHASE DETECTOR
1
2
4
8
MR
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8432BYI-51
www.icst.com/products/hiperclocks.html
REV. A MAY 28, 2003
2
Integrated
Circuit
Systems, Inc.
ICS8432I-51
700MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
M divider and N output divider to a specific default state that
will automatically occur during power-up. The TEST output is
LOW when operating in the parallel input mode. The relationship
between the VCO frequency, the crystal frequency and the
M divider is defined as follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 10
M
28. The frequency
out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-to-
LOW transition of S_LOAD. If S_LOAD is held HIGH, data at
the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS8432I-51 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 250MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8432I-51 support two in-
put modes to program the M divider and N output divider. The
two input operational modes are parallel and serial.
Figure 1
shows the timing diagram for each mode. In parallel mode, the
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 and N0 and N1 is passed directly to the M divider and N
output divider. On the LOW-to-HIGH transition of the nP_LOAD
input, the data is latched and the M divider remains loaded until
the next LOW transition on nP_LOAD or until a serial event
occurs. As a result, the M and N bits can be hardwired to set the
fVCO = fxtal x M
T1
T0
TEST Output
0
0
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
1
CMOS Fout
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
*NOTE: The NULL timing slot must be observed.
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
M, N
t
S
t
H
t
S
t
H
t
S
T 1
T0
*NULL
N 1
N 0
M8
M7
M6
M5
M4
M3
M2
M1
M 0
FOUT = fVCO = fxtal x M
N
N
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
8432BYI-51
www.icst.com/products/hiperclocks.html
REV. A MAY 28, 2003
3
Integrated
Circuit
Systems, Inc.
ICS8432I-51
700MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
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8432BYI-51
www.icst.com/products/hiperclocks.html
REV. A MAY 28, 2003
4
Integrated
Circuit
Systems, Inc.
ICS8432I-51
700MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
s
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3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
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T
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ROGRAMMABLE
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UTPUT
D
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UNCTION
T
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8432BYI-51
www.icst.com/products/hiperclocks.html
REV. A MAY 28, 2003
5
Integrated
Circuit
Systems, Inc.
ICS8432I-51
700MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= -40C
TO
85C
l
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b
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=
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L
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1
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p
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g
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1
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T
O
N
;
T
S
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T
6
.
2
V
V
L
O
t
u
p
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a
t
l
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w
o
L
1
E
T
O
N
;
T
S
E
T
5
.
0
V
NOTE 1: Outputs terminated with 50
to V
CCO
/2.
l
o
b
m
y
S
r
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t
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m
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a
P
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3
.
3
5
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3
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n
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r
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p
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l
p
p
u
S
g
o
l
a
n
A
5
1
A
m
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8432BYI-51
www.icst.com/products/hiperclocks.html
REV. A MAY 28, 2003
6
Integrated
Circuit
Systems, Inc.
ICS8432I-51
700MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
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t
e
m
a
r
a
P
s
n
o
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s
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m
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m
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l
a
c
i
p
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T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
O
1
E
T
O
N
;
e
g
a
t
l
o
V
h
g
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t
u
p
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u
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C
C
4
.
1
-
V
O
C
C
0
.
1
-
V
V
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1
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T
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N
;
e
g
a
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0
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2
-
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C
7
.
1
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6
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1
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t
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:
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3
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r
u
g
i
f
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= -40C
TO
85C
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HARACTERISTICS
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T
ABLE
7. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= -40C
TO
85C
8432BYI-51
www.icst.com/products/hiperclocks.html
REV. A MAY 28, 2003
7
Integrated
Circuit
Systems, Inc.
ICS8432I-51
700MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
S
KEW
SCOPE
Qx
nQx
LVPECL
V
CC
, V
CCA
, V
CCO
= 2V
V
EE
= -1.3V 0.165V
tsk(o)
nFOUTx
FOUTx
nFOUTy
FOUTy
C
YCLE
-
TO
-C
YCLE
J
ITTER
P
ERIOD
J
ITTER
FOUTx
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
contains 68.26% of all measurements
2
contains 95.4% of all measurements
3
contains 99.73% of all measurements
4
contains 99.99366% of all measurements
6
contains (100-1.973x10
-7
)% of all measurements
Histogram
nFOUTx
FOUTx
nFOUTx
odc & t
P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
8432BYI-51
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REV. A MAY 28, 2003
8
Integrated
Circuit
Systems, Inc.
ICS8432I-51
700MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
Table 8. Common SANs Application Frequencies
Table 9. Configuration Details for SANs Applications
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8432I-51 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2 illustrates how
a 10
resistor along with a 10
F and a .01
F bypass
capacitor should be connected to each V
CCA
pin.
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
y
g
o
l
o
n
h
c
e
T
t
c
e
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n
o
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I
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t
a
R
k
c
o
l
C
S
E
D
R
E
S
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y
c
n
e
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F
e
c
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f
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R
)
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H
M
(
y
c
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F
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a
t
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C
)
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H
M
(
t
e
n
r
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t
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b
a
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G
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H
G
5
2
.
1
5
2
.
6
5
1
,
0
5
2
,
5
2
1
5
2
1
3
5
.
9
1
,
5
2
l
e
n
n
a
h
C
e
r
b
i
F
z
H
G
5
2
6
0
.
1
1
C
F
z
H
G
0
5
2
1
.
2
2
C
F
5
2
1
8
.
2
3
1
,
5
2
1
.
3
5
,
5
2
.
6
0
1
5
2
,
5
2
6
5
1
0
6
.
6
1
d
n
a
b
i
n
i
f
n
I
z
H
G
5
.
2
0
5
2
,
5
2
1
5
2
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
S
TORAGE
A
REA
N
ETWORKS
A variety of technologies are used for interconnection of the
elements within a SAN. The tables below lists the common
frequencies used as well as the settings for the ICS8432I-51
to generate the appropriate frequency.
t
c
e
n
n
o
c
r
e
t
n
I
y
g
o
l
o
n
h
c
e
T
y
c
n
e
u
q
e
r
F
l
a
t
s
y
r
C
)
z
H
M
(
1
5
-
I
2
3
4
8
S
C
I
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
S
E
D
R
E
S
o
t
)
z
H
M
(
1
5
-
I
2
3
4
8
S
C
I
s
g
n
i
t
t
e
S
N
&
M
8
M
7
M
6
M
5
M
4
M
3
M
2
M
1
M
0
M
1
N
0
N
t
e
n
r
e
h
t
E
t
i
b
a
g
i
G
5
2
5
2
1
0
0
0
0
1
0
1
0
0
1
0
5
2
0
5
2
0
0
0
0
1
0
1
0
0
0
1
5
2
5
2
.
6
5
1
0
0
0
0
1
1
0
0
1
1
0
5
2
1
3
5
.
9
1
5
2
.
6
5
1
0
0
0
1
0
0
0
0
0
1
0
1
l
e
n
n
a
h
C
r
e
b
i
F
5
2
5
2
1
.
3
5
0
0
0
0
1
0
0
0
1
1
1
5
2
5
2
.
6
0
1
0
0
0
0
1
0
0
0
1
1
0
2
l
e
n
n
a
h
C
r
e
b
i
F
5
2
6
5
1
0
6
.
6
1
5
2
1
8
.
2
3
1
0
0
0
1
0
0
0
0
0
1
0
d
n
a
b
i
n
i
f
n
I
5
2
5
2
1
0
0
0
0
1
0
1
0
0
1
0
5
2
0
5
2
0
0
0
0
1
0
1
0
0
0
1
8432BYI-51
www.icst.com/products/hiperclocks.html
REV. A MAY 28, 2003
9
Integrated
Circuit
Systems, Inc.
ICS8432I-51
700MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
Figure 3. C
RYSTAL
I
NPU
t I
NTERFACE
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUTx and nFOUTx are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
4B. LVPECL O
UTPUT
T
ERMINATION
3.3V
F
OUT
F
IN
5
2 Z
o
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o
= 50
Z
o
= 50
F
IGURE
4A. LVPECL O
UTPUT
T
ERMINATION
RTT =
1
(V
OH
+ V
OL
/ V
CC
2) 2
Z
o
Z
o
= 50
Z
o
= 50
50
50
RTT
V
CC
- 2V
F
IN
F
OUT
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS8432I-51 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in
Figure 3 below
were determined using a 25MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error. The optimum C1 and C2
values can be slightly adjusted for different board layouts.
C1
22p
X1
18pF Parallel Cry stal
C2
22p
XTAL2
XTAL1
8432BYI-51
www.icst.com/products/hiperclocks.html
REV. A MAY 28, 2003
10
Integrated
Circuit
Systems, Inc.
ICS8432I-51
700MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
F
IGURE
5A. S
CHEMATIC
OF
R
ECOMMENDED
L
AYOUT
L
AYOUT
G
UIDELINE
The schematic of the ICS8432I-51 layout example used in
this layout guideline is shown in
Figure 5A. The ICS8432I-51
recommended PCB board layout for this example is shown in
Figure 5B. This layout example is used as a general guideline.
The layout in the actual system will depend on the selected
component types, the density of the components, the density
of the traces, and the stack up of the P.C. board.
S_LOAD
R4
84
C2
C15
0.1u
R7
10
R1
125
C14
0.1u
S_CLOCK
FO
U
T
N
REF_IN
C16
10u
X1
S_DATA
VCC
VCC
FO
UT
XTAL_SEL
TL1
Zo = 50 Ohm
VCCA
VC
C
VC
C
C11
0.01u
R3
125
R2
84
C1
+
-
U1
ICS8432I-51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
M5
M6
M7
M8
N0
N1
nc
VEE
TE
S
T
VC
C
FO
U
T
1
nF
OU
T
1
V
CCO
FO
U
T
0
nF
OU
T
0
VE
E
MR
S_CLOCK
S_DATA
S_LOAD
VCCA
nXTAL_SEL
REF_IN
XTAL2
M4
M3
M2
M1
M0
VC
O
_
SE
L
nP
_LO
AD
XT
A
L
1
TL2
Zo = 50 Ohm
8432BYI-51
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REV. A MAY 28, 2003
11
Integrated
Circuit
Systems, Inc.
ICS8432I-51
700MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
F
IGURE
5B. PCB B
OARD
L
AYOUT
FOR
ICS8432I-51
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C14 and C15, as close as pos-
sible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
CCA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have the
same length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL2) and 25 (XTAL1). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
C14
C16
C15
VIA
PIN 1
VCCA
TL1, TL21N are 50 Ohm
traces and equal length
C11
R4
TL1
T
L1N
R2
GND
R1
R3
C1
Close to the input
pins of the
receiver
R7
VCC
U1
TL
1
C2
TL1N
X1
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REV. A MAY 28, 2003
12
Integrated
Circuit
Systems, Inc.
ICS8432I-51
700MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8432I-51.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8432I-51 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 135mA = 467.8mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power
_MAX
(3.465V, with all outputs switching) = 467.8mW + 60.4mW = 528.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 10 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.528W * 42.1C/W = 107.2C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
10. T
HERMAL
R
ESISTANCE
q
JA
FOR
32-
PIN
LQFP, F
ORCED
C
ONVECTION
8432BYI-51
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REV. A MAY 28, 2003
13
Integrated
Circuit
Systems, Inc.
ICS8432I-51
700MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
1.0V
(V
CCO_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
) * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
6. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
8432BYI-51
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REV. A MAY 28, 2003
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Integrated
Circuit
Systems, Inc.
ICS8432I-51
700MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8432I-51 is: 3743
T
ABLE
11.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8432BYI-51
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REV. A MAY 28, 2003
15
Integrated
Circuit
Systems, Inc.
ICS8432I-51
700MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ACKAGE
O
UTLINE
- Y S
UFFIX
T
ABLE
12. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
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8432BYI-51
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REV. A MAY 28, 2003
16
Integrated
Circuit
Systems, Inc.
ICS8432I-51
700MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
13. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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