Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignments
- Functional Description
- Parallel & Serial Load Operations
- Pin Descriptions
- Pin Characteristics
- Parallel & Serial Mode Function Table
- Programmable VCO Frequency Function Table
- Programmable Output Divider Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Crystal Characteristics
- Input Frequency Characteristics
- AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- Period Jitter Diagram
- Cycle-to-Cycle Jitter Diagram
- Output Rise/Fall Time Diagram
- odc & tPeriod Diagram
- Application Information
- Power Supply Filtering Techniques
- Power Supply Filtering Diagram
- Termination for LVPECL Outputs
- LVPECL Output Termination Diagrams
- LVCMOS to XTAL Interface
- General Diagram for LVCMOS Driver to XTAL Input Interface Diagram
- Cycle-to-Cycle Jitter vs. fOUT Diagram
- Layout Guideline
- Schematic of Recommended Layout
- Power & Grounding
- Clock Traces & Termination
- Crystal
- PCB Board Layout
- Jitter Reduction for FREF_EXT Single End Input
- Amplitude Reduction for a Long Trace Diagram
- Amplitude Reduction for a Short Trace Diagram
- Edge Rate Reduction by Increasing the Resistor Value Diagram
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance for 28-Pin PLCC
- Thermal Resistance for 32-Pin LQFP
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- PLCC Package Outline
- PLCC Package Dimensions
- LQFP Package Outline
- LQFP Package Dimensions
- Ordering Information
- Revision History Sheet
84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
1
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS84330 is a general purpose, single output
high frequency synthesizer and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The VCO operates at a fre-
quency range of 250MHz to 700MHz. The VCO and
output frequency can be programmed using the serial or parallel
interfaces to the configuration logic. The output can be config-
ured to divide the VCO frequency by 1, 2, 4, and 8. Output fre-
quency steps from 250KHz to 2MHz can be achieved using a
16MHz crystal depending on the output divider setting.
F
EATURES
Fully integrated PLL, no external loop filter requirements
1 differential 3.3V LVPECL output
Crystal oscillator interface: 10MHz to 25MHz
Output frequency range: 25MHz to 700MHz
VCO range: 250MHz to 700MHz
Parallel or serial interface for programming M and N dividers
during power-up
RMS Period jitter: 5ps (maximum)
Cycle-to-cycle jitter: 40ps (maximum)
3.3V supply voltage
0C to 70C ambient operating temperature
Pin compatible with the MC12430
Industrial temperature information available upon request
HiPerClockSTM
,&6
P
IN
A
SSIGNMENT
B
LOCK
D
IAGRAM
ICS84330
28-Lead PLCC
V Package
11.6mm x 11.4mm x 4.1mm
body package
Top View
25 24 23 22 21 20 19
5 6 7 8 9 10 11
26
27
28
1
2
3
4
18
17
16
15
14
13
12
S_CLOCK
S_DATA
S_LOAD
V
CCA
FREF_EXT
XTAL_SEL
XTAL1
M3
M2
M1
M0
nP_LOAD
OE
X
T
AL2
V
EE
TEST
V
CC
V
EE
nFOUT
FOUT
V
CC
N 1
N 0
M8
M7
M6
M5
M4
OSC
XTAL1
XTAL2
FREF_EXT
XTAL_SEL
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
VCO
PLL
TEST
CONFIGURATION
INTERFACE
LOGIC
M
16
PHASE DETECTOR
2
4
8
1
1
0
OE
1
0
2
FOUT
nFOUT
ICS84330
32-Lead LQFP
Y package
7mm x 7mm x 1.4mm
body package
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
n/c
N 1
N 0
M8
M7
M6
M5
M4
S_CLOCK
S_DATA
S_LOAD
V
CCA
V
CCA
FREF_EXT
XTAL_SEL
XTAL1
nc
M3
M2
M1
M0
nP_LOAD
OE
X
T
AL2
V
EE
TEST
V
CC
V
CC
V
EE
nFOUT
FOUT
V
CC
84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
2
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 6, NOTE 1.
The ICS84330 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth.
A quartz crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase
detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of
250MHz to 700MHz. The output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency
by adjusting the
VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS84330 support two input modes to program the M divider and N output divider. The two input
operational modes are parallel and serial.
Figure 1 shows the timing diagram for each mode. In parallel mode the nP_LOAD input
is LOW. The data on inputs M0 through M8 and N0 through N1 is passed directly to the M divider and N output divider. On the LOW-
to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. The TEST output is Mode 000 (shift register out) when operating in the parallel input mode.
The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows:
The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock are defined as 125
M
350. The frequency out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the
S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD.
If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider on each rising edge of S_CLOCK. The
serial mode can be used to program the M and N bits and test bits T2:T0. The internal registers T2:T0 determine the state of
the TEST output as follows:
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
16
2M
fVCO =
fxtal x
N
fout =
fVCO
=
16
2M
fxtal x
N
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
M, N
t
S
t
H
t
S
t
H
t
S
T2
T1
T0
TEST Output
0
0
0
Shift Register Out
0
0
1
High
0
1
0
PLL Reference Xtal 16
0
1
1
(VCO M) /2 (non 50% Duty Cycle M divider)
1
0
0
fOUT
LVCMOS Output Frequency < 200MHz
1
0
1
Low
1
1
0
(S_CLOCK M) /2 (non 50% Duty Cycle M divider)
1
1
1
fOUT 4
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
S_CLOCK N divider
fOUT
T2
T1
T0
N 1
N 0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
3
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
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K
84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
4
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
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84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
5
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, T
A
= 0C
TO
70C
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,
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A
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TO
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ABLE
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HARACTERISTICS
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CCA
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N
;
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a
t
l
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o
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:
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2
/
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
6
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
6. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, T
A
= 0C
TO
70C
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84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
7
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
SCOPE
Qx
nQx
LVPECL
C
YCLE
-
TO
-C
YCLE
J
ITTER
P
ERIOD
J
ITTER
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
V
CC,
V
CCA
= 2V
V
EE
= -1.3V 0.165V
FOUT
O
UTPUT
R
ISE
/F
ALL
T
IME
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
odc & tP
ERIOD
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
contains 68.26% of all measurements
2
contains 95.4% of all measurements
3
contains 99.73% of all measurements
4
contains 99.99366% of all measurements
6
contains (100-1.973x10
-7
)% of all measurements
Histogram
nFOUT
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
FOUT
nFOUT
Clock Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
8
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
3.3V
F
OUT
F
IN
5
2 Z
o
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o
= 50
Z
o
= 50
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
RTT =
1
(V
OH
+ V
OL
/ V
CC
2) 2
Z
o
50
50
RTT
V
CC
- 2V
F
IN
F
OUT
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
Z
o
= 50
Z
o
= 50
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84330 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
and V
CCA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2 illustrates how
a 10
resistor along with a 10
F and a .01
F bypass
capacitor should be connected to each V
CCA
pin.
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
9
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
50
40
30
20
10
0
200
300
600
700
400
500
Output Frequency (MHz)
Cyc
le-to-Cyc
le Jitter (ps)
N = 1
Spec Limit
LVCMOS
TO
XTAL I
NTERFACE
The XTAL1 input can accept single ended LVCMOS signal
through an AC couple capacitor. A general interface diagram
is shown in
Figure 4. The XTAL2 input can be left floating. The
edge rate can be as slow as 10ns. If the incoming signal has
sharp edge rate and the signal path is a long trace, proper
termination for the driver and controlled characteristic imped-
Crystal Input Interface
XTAL1
XTAL2
C1
0.1uF
Q1
LVCMOS_Driver
VDD
Figure 4. G
ENERAL
D
IAGRAM
FOR
LVCMOS D
RIVER
TO
XTAL I
NPUT
I
NTERFACE
ance trace may be required. The input can function with half
swing amplitude. Reducing amplitude from full swing of 3.3V
to half swing of about 1.65V can prevent signal interfere with
power rail and may reduce noise. Please refer to the LVCMOS
driver data sheet and application note for amplitude reduction
and termination approach.
F
IGURE
5. C
YCLE
-
TO
-C
YCLE
J
ITTER
VS
. fOUT
(using a 16MHz XTAL)
84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
10
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
The schematic of the ICS84330 layout example used in
this layout guideline is shown in
Figure 6A. The ICS84330
recommended PCB board layout for this example is shown
in
Figure 6B. This layout example is used as a general guide-
L
AYOUT
G
UIDELINE
F
IGURE
6A. S
CHEMATIC
OF
R
ECOMMENDED
L
AYOUT
line. The layout in the actual system will depend on the
selected component types, the density of the components,
the density of the traces, and the stack up of the P.C. board.
M7
C4
0.1u
M8
M5
n
P
Lo
ad
VCCA
OE
C3
0.1uF
S P = S p a ce (i.e . n o t i n tsta ll e d )
M6
M8
M3
Fo u t = 2 0 0 M Hz
RU0
SP
N0
nP
L
O
A
D
Zo = 50 Ohm
VC
C
N[1 :0 ] =0 0 (Divid e b y 2 )
M4
M2
R1
50
N1
N1
M0
U1
ICS84330
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
27
26
25
24
23
22
21
28
VCCA
FREF_EXT
XTAL_SEL
XTAL1
XT
AL
2
OE
nP
_LO
AD
M0
M1
M2
M3
M4
M5
M6
M7
M8
N0
N1
VE
E
T
EST
S_DATA
S_CLOCK
VC
C
FO
U
T
nF
O
U
T
VE
E
VC
C
S_LOAD
VCC
R2
50
RD9
1K
N2
V CC=3 .3 V
RU7
1K
RU1
SP
RD7
SP
Zo = 50 Ohm
M0
RU10
1K
VCC
RD10
SP
C1
SP
C11
0.01u
M1
OE
R7
10
+
-
RU11
SP
RU9
SP
X1
16MHz, 18pF
RU8
1K
RD6
1K
RU12
1K
M7
R3
50
RD12
SP
RD1
1K
RD0
1K
C2
SP
M1
C16
10u
RD8
SP
M [8 :0 ]= 1 1 0 0 1 0 0 0 0 (4 0 0 )
84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
11
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
F
IGURE
6B. PCB B
OARD
L
AYOUT
FOR
ICS84330
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C3 and C4, as close as pos-
sible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
CCA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have the
same length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
4 (XTAL1) and 5 (XTAL2). The trace length between the X1 and
U1 should be kept to a minimum to avoid unwanted parasitic in-
ductance and capacitance. Other signal traces should not be
routed near the crystal traces.
R7
Signals
Traces
VCCA
C1
C4
VCC
50 Ohm
Traces
C11
C3
GND
PIN 2
C2
PIN 1
C16
U1
X1
VIA
VCCA
84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
12
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
If the FREF_EXT input is driven by a 3.3V LVCMOS driver, the
jitter performance can be improved by reducing the amplitude
swing and slowing down the edge rate.
Figure 7A shows an
amplitude reduction approach for a long trace. The swing will
be approximately 0.85V for logic low and 2.5V for logic high
R2
100
VDD
R1
100
Ro ~ 7 Ohm
Driver_LVCMOS
Zo = 50 Ohm
Td
RS
43
VDD
VDD
GND
TEST_CLK
VDD
VDD
GND
TEST_CLK
R1
200
RS
100
Ro ~ 7 Ohm
Driver_LVCMOS
R2
200
VDD
VDD
VDD
R1
400
R2
400
Ro ~ 7 Ohm
Driver_LVCMOS
RS
200
VDD
GND
TEST_CLK
J
ITTER
R
EDUCTION
FOR
FREF_EXT S
INGLE
E
ND
I
NPUT
(instead of 0V to 3.3V).
Figure 7B shows amplitude reduction
approach for a short trace. The circuit shown in
Figure 7C
reduces amplitude swing and also slows down the edge rate
by increasing the resistor value.
F
IGURE
7C. E
DGE
R
ATE
R
EDUCTION
BY
I
NCREASING
THE
R
ESISTOR
V
ALUE
F
IGURE
7A. A
MPLITUDE
R
EDUCTION
FOR
A
L
ONG
T
RACE
F
IGURE
7B. A
MPLITUDE
R
EDUCTION
FOR
A
S
HORT
T
RACE
FREF_EXT
FREF_EXT
FREF_EXT
84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
13
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8C/W
31.1C/W
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
9A. T
HERMAL
R
ESISTANCE
q
JA
FOR
28-
PIN
PLCC, F
ORCED
C
ONVECTION
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
9B. T
HERMAL
R
ESISTANCE
q
JA
FOR
32-
PIN
LQFP, F
ORCED
C
ONVECTION
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84330.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84330 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 145mA = 502.4mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 1 * 30.2mW = 30.2mW
Total Power
_MAX
(3.465V, with all outputs switching) = 502.4 + 30.2mW = 532.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1C/W per Table 9A below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.533W * 31.1C/W = 86.6C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
14
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in the
Figure 8.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
1.0V
(V
CC_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CC_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
8. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
15
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8C/W
31.1C/W
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS84330 is: 4442
T
ABLE
10A.
JA
VS
. A
IR
F
LOW
PLCC T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
10B.
JA
VS
. A
IR
F
LOW
LQFP T
ABLE
84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
16
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- V S
UFFIX
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Reference Document: JEDEC Publication 95, MS-018
84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
17
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
T
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11B. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
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84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
18
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
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While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
84330BV
www.icst.com/products/hiperclocks.html
REV. B MAY 5, 2003
19
Integrated
Circuit
Systems, Inc.
ICS84330
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
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