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Электронный компонент: ICS84330AV-01

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84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
1
Integrated
Circuit
Systems, Inc.
ICS84330-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS84330-01 is a general purpose, single out-
put high frequency synthesizer and a member of
the HiPerClockSTM family of High Performance Clock
Solutions from ICS. The VCO operates at a fre-
quency range of 200MHz to 700MHz. The VCO
and output frequency can be programmed using the serial or
parallel interfaces to the configuration logic. The output can be
configured to divide the VCO frequency by 1, 2, 4, and 8. Out-
put frequency steps from 250KHz to 2MHz can be achieved
using a 16MHz crystal depending on the output divider setting.
F
EATURES
Fully integrated PLL, no external loop filter requirements
1 differential 3.3V LVPECL output
Crystal oscillator interface: 10MHz to 25MHz
Output frequency range: 25MHz to 700MHz
VCO range: 200MHz to 700MHz
Parallel or serial interface for programming M and N dividers
during power-up
RMS Period jitter: TBD
Cycle-to-cycle jitter: 15ps (typical)
3.3V supply voltage
0C to 70C ambient operating temperature
Pin compatible with the SY89430V
HiPerClockSTM
,&6
P
IN
A
SSIGNMENT
B
LOCK
D
IAGRAM
S_CLOCK
S_DATA
S_LOAD
V
CCA
nc
nc
XTAL1
ICS84330-01
28-Lead PLCC
V Package
11.6mm x 11.4mm x 4.1mm
Top View
25 24 23 22 21 20 19
5 6 7 8 9 10 11
26
27
28
1
2
3
4
18
17
16
15
14
13
12
M3
M2
M1
M0
nP_LOAD
V
CC
X
T
AL2
V
EE
TEST
V
CC
V
EE
nFOUT
FOUT
V
CCO
N 1
N 0
M8
M7
M6
M5
M4
ICS84330-01
28-Lead SOIC
7.5mm x 18.05mm x 2.25mm body package
M Package
Top View
M0
M1
M2
M3
M4
M5
M6
M7
M8
N 0
N 1
V
EE
TEST
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nP_LOAD
V
CC
XTAL2
XTAL1
nc
nc
V
CCA
S_LOAD
S_DATA
S_CLOCK
V
CCO
FOUT
nFOUT
V
EE
FOUT
nFOUT
OSC
XTAL1
XTAL2
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
VCO
PLL
TEST
CONFIGURATION
INTERFACE
LOGIC
M
16
PHASE DETECTOR
N
1
0
2
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
2
Integrated
Circuit
Systems, Inc.
ICS84330-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 6, NOTE 1.
The ICS84330-01 features a fully integrated PLL and therefore requires no external components for setting the loop band-
width. A quartz crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the
phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates over a range
of 200MHz to 700MHz. The output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency divided by 16 by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output
duty cycle.
The programmable features of the ICS84330-01 support two input modes to program the M divider and N output divider. The two
input operational modes are parallel and serial.
Figure 1 shows the timing diagram for each mode. In parallel mode the nP_LOAD
input is LOW. The data on inputs M0 through M8 and N0 through N1 is passed directly to the M divider and N output divider. On the
LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition
on nP_LOAD or until a serial event occurs. The TEST output is Mode 000 (shift register out) when operating in the parallel input
mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows:
The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock are defined as 100
M
350. The frequency out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits
with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider when S_LOAD transitions from
LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held
HIGH, data at the S_DATA input is passed directly to the M divider on each rising edge of S_CLOCK. The serial mode can be used
to program the M and N bits and test bits T2:T0. The internal registers T2:T0 determine the state of the TEST output as follows:
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
M, N
t
S
t
H
t
S
t
H
t
S
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
16
2M
fVCO =
fxtal x
N
fout =
fVCO
=
16
2M
fxtal x
N
T2
T1
T0
TEST Output
0
0
0
Shift Register Out
0
0
1
High
0
1
0
PLL Reference Xtal 16
0
1
1
(VCO M) /2 (non 50% Duty M divider)
1
0
0
fOUT
LVCMOS Output Frequency < 200MHz
1
0
1
Low
1
1
0
(S_CLOCK M) /2 (non 50% Duty Cycle M divider)
1
1
1
fOUT 4
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
S_CLOCK N divider
fOUT
T2
T1
T0
N 1
N 0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
3
Integrated
Circuit
Systems, Inc.
ICS84330-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
1. P
IN
D
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84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
4
Integrated
Circuit
Systems, Inc.
ICS84330-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
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=
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
5
Integrated
Circuit
Systems, Inc.
ICS84330-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
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t
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m
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V
H
O
1
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O
N
;
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h
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C
C
4
.
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-
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C
C
0
.
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-
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V
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;
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C
.
V
2
-
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
l
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O
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;
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g
a
t
l
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h
g
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H
t
u
p
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6
.
2
V
V
L
O
1
E
T
O
N
;
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
5
.
0
V
0
5
h
t
i
w
d
e
t
a
n
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m
r
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t
s
t
u
p
t
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:
1
E
T
O
N
V
o
t
O
C
C
.
2
/
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, V
O
-0.5V to V
CCO
+ 0.5V
Package Thermal Impedance,
JA
37.8C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
6
Integrated
Circuit
Systems, Inc.
ICS84330-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
6. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
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m
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.
4
2
2
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
r
e
t
e
m
a
r
a
P
s
n
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F
p
T
ABLE
7. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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N
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
7
Integrated
Circuit
Systems, Inc.
ICS84330-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
P
ERIOD
J
ITTER
C
YCLE
-
TO
-C
YCLE
J
ITTER
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
V
CC
, V
CCA
, V
CCO
= 2V
odc & t
P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
contains 68.26% of all measurements
2
contains 95.4% of all measurements
3
contains 99.73% of all measurements
4
contains 99.99366% of all measurements
6
contains (100-1.973x10
-7
)% of all measurements
Histogram
V
EE
= -1.3V 0.165V
Clock Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
FOUT
nFOUT
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
nFOUT
FOUT
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
8
Integrated
Circuit
Systems, Inc.
ICS84330-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
3.3V
F
OUT
F
IN
5
2 Z
o
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o
= 50
Z
o
= 50
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
RTT =
1
(V
OH
+ V
OL
/ V
CC
2) 2
Z
o
50
50
RTT
V
CC
- 2V
F
IN
F
OUT
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84330-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
and V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2 illustrates how
a 10
resistor along with a 10
F and a .01
F bypass
capacitor should be connected to each V
CCA
pin.
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
Z
o
= 50
Z
o
= 50
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
9
Integrated
Circuit
Systems, Inc.
ICS84330-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8C/W
31.1C/W
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
8A. T
HERMAL
R
ESISTANCE
q
JA
FOR
28-
PIN
PLCC, F
ORCED
C
ONVECTION
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
76.2C/W
60.8C/W
53.2C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2C/W
39.7C/W
36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
8B. T
HERMAL
R
ESISTANCE
q
JA
FOR
28-
PIN
SOIC, F
ORCED
C
ONVECTION
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84330-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84330-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 115mA = 398.5mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 1 * 30.2mW = 30.2mW
Total Power
_MAX
(3.465V, with all outputs switching) = 398.5mW + 30.2mW = 428.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1C/W per Table 8A below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.429W * 31.1C/W = 83.3C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
10
Integrated
Circuit
Systems, Inc.
ICS84330-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in the
Figure 4.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
1.0V
(V
CCO_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
4. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
11
Integrated
Circuit
Systems, Inc.
ICS84330-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8C/W
31.1C/W
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS84330-01 is: 4442
T
ABLE
9A.
JA
VS
. A
IR
F
LOW
PLCC T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
76.2C/W
60.8C/W
53.2C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2C/W
39.7C/W
36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
9B.
JA
VS
. A
IR
F
LOW
SOIC T
ABLE
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
12
Integrated
Circuit
Systems, Inc.
ICS84330-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ACKAGE
O
UTLINE
- V S
UFFIX
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
M
U
M
I
N
I
M
M
U
M
I
X
A
M
N
8
2
A
9
1
.
4
7
5
.
4
1
A
9
2
.
2
5
0
.
3
2
A
7
5
.
1
1
1
.
2
b
3
3
.
0
3
5
.
0
c
9
1
.
0
2
3
.
0
D
2
3
.
2
1
7
5
.
2
1
1
D
3
4
.
1
1
8
5
.
1
1
2
D
5
8
.
4
6
5
.
5
E
2
3
.
2
1
7
5
.
2
1
1
E
3
4
.
1
1
8
5
.
1
1
2
E
5
8
.
4
6
5
.
5
T
ABLE
10A. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-018
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
13
Integrated
Circuit
Systems, Inc.
ICS84330-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ACKAGE
O
UTLINE
- M S
UFFIX
T
ABLE
10B. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-013, MO-119
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
M
U
M
I
N
I
M
M
U
M
I
X
A
M
N
8
2
A
-
-
5
6
.
2
1
A
0
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.
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2
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5
0
.
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3
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.
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2
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1
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8
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
14
Integrated
Circuit
Systems, Inc.
ICS84330-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
11. O
RDERING
I
NFORMATION
r
e
b
m
u
N
r
e
d
r
O
/
t
r
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p
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1
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-
V
A
0
3
3
4
8
S
C
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V
A
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3
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While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.