843404AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 17, 2005
1
Integrated
Circuit
Systems, Inc.
ICS843404
LVCMOS/C
RYSTAL
-
TO
-3.3V LVPECL
AND
LVDS C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS843404 is a low phase noise Fibre
Channel Clock Generator and is a member of
the HiPerClockS
TM
family of high performance
clock solutions from ICS. The device provides
two banks of one LVPECL output per bank and
one bank of two LVDS outputs. Each bank can be
independently set by using their respective frequency select
pins for the following output frequencies: 318.75MHz,
212.5MHz, 159.375MHz or 106.25MHz, using a 25.5MHz
18pF parallel resonant crystal. The ICS843404 can also be
driven from a 25.5MHz single-ended reference clock. For
system debug or test purposes, the PLL can be bypassed
using the VCO_SEL pin.
F
EATURES
Three banks of outputs: one bank of two LVDS outputs
and two banks of one LVPECL output
Selectable crystal oscillator interface or
LVCMOS/LVTTL single-ended reference clock input
Four independently selectable output frequency on each
bank: 318.75MHz, 212.5MHz, 159.375MHz and 106.25MHz
Maximum output frequency: 318.75MHz
Crystal input frequency: 25.5MHz
V
DDO
_LVPECL can be set for 3.3V or 2.5V, allowing the
device to generate 3.3V or 2.5V LVPECL levels
RMS phase jitter at 106.25MHz, using a 25.5MHz crystal
(637kHz to 10MHz intergration): 2.65ps (typical)
Offset
Noise Power
100Hz ................. -89.1 dBc/Hz
1kHz ................. -112.7 dBc/Hz
10kHz ................. -128.0 dBc/Hz
100kHz ................. -130.2 dBc/Hz
Supply voltage modes:
V
DD
= V
DDA
= 3.3V
V
DDO_
LVPECL = 3.3V or 2.5V
V
DDO_
LVDS = 3.3V
0C to 70C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
Industrial termperature information available upon request
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
0
1
0
1
Phase
Detector
VCO
637.5MHz
(Fixed)
M = 25 (fixed)
LVDS_FSEL1:0
0 0 2
0 1 3
1 0 4
1 1 6
LVPECL_FSELA1:0
0 0 2
0 1 3
1 0 4
1 1 6
LVPECL_FSELB1:0
0 0 2
0 1 3
1 0 4
1 1 6
25.5MHz
V
DDO
_LVPECL
V
DDO
_LVDS
OSC
B
LOCK
D
IAGRAM
VCO_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
XTAL_SEL
MR
LVPECLA0
nLVPECLA0
LVPECLB0
nLVPECLB0
LVDS0
nLVDS0
LVDS1
nLVDS1
Pullup
Pulldown
Pullup
Pulldown
ICS843404
28-Lead TSSOP, 173-MIL
4.4mm x 9.7mm x 0.92mm
body package
G Package
Top View
MR
VCO_SEL
V
DD
o_LVDS
LVDS0
nLVDS0
LVDS1
nLVDS1
nc
LVPECL_FSELB0
LVPECL_FSELB1
nc
V
DDA
LVPECL_FSELA0
V
DD
LVDS_FSEL0
LVDS_FSEL1
V
DDO
_LVPECL
LVPECLA0
nLVPECLA0
LVPECLB0
nLVPECLB0
XTAL_SEL
TEST_CLK
GND
GND
XTAL_IN
XTAL_OUT
LVPECL_FSELA1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
843404AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 17, 2005
4
Integrated
Circuit
Systems, Inc.
ICS843404
LVCMOS/C
RYSTAL
-
TO
-3.3V LVPECL
AND
LVDS C
LOCK
G
ENERATOR
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO_LVPECL
= V
DDO_LVDS
= 3.3V5%, TA = 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
(LVPECL Outputs)
Continuous Current
50mA
Surge Current
100mA
Outputs, I
O
(LVDS Outputs)
Continuous Current
10mA
Surge Current
15mA
Package Thermal Impedance,
JA
49.8C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO_LVPECL
= 2.5V5%, TA = 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
e
r
o
C
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
A
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
g
o
l
a
n
A
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
L
C
E
P
V
L
_
O
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
t
u
p
t
u
O
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
S
D
V
L
_
O
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
t
u
p
t
u
O
5
3
1
.
3
3
.
3
5
6
4
.
3
V
I
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
0
0
1
A
m
I
A
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
g
o
l
a
n
A
5
2
A
m
I
L
C
E
P
V
L
_
O
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
t
u
p
t
u
O
0
2
A
m
I
S
D
V
L
_
O
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
t
u
p
t
u
O
5
5
A
m
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
e
r
o
C
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
A
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
g
o
l
a
n
A
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
L
C
E
P
V
L
_
O
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
t
u
p
t
u
O
5
7
3
.
2
5
.
2
5
2
6
.
2
V
I
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
0
7
A
m
I
A
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
g
o
l
a
n
A
0
2
A
m
I
L
C
E
P
V
L
_
O
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
t
u
p
t
u
O
0
2
A
m
PDF 
ZIP
