Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Output Configuration and Frequency Range Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVDS DC Characteristics
- Crystal Characteristics
- AC Characteristics
- Typical Phase Noise Plot @ 155.52MHz
- Typical Phase Noise Plot @ 622.08MHz
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- 3.3V LVDS Driver Termination
- Recommendations for Unused Input and Output Pins
- Schematic Example
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
844004AGI-04
www.icst.com/products/hiperclocks.html
REV. A JANUARY 26, 2006
1
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
0
1
Phase
Detector
VCO
M = 32
OSC
4
1
0
1
0
1
0
1
0
1
G
ENERAL
D
ESCRIPTION
T h e I C S 8 4 4 0 0 4 I - 0 4 i s a 4 o u t p u t LV D S
Synthesizer optimized to generate clock
frequencies for a variety of high performance
a p p l i c a t i o n s a n d i s a m e m b e r o f t h e
HiPerClocks
TM
family of high perfor mance
clock solutions from ICS. This device can select its input
reference clock from either a crystal input or a single-
ended clock signal. It can be configured to generate 4
outputs with individually selectable divide-by-one or
divide-by-four function via the 4 frequency select pins
(F_SEL[3:0]). The ICS844004I-04 uses ICS' 3
rd
generation
low phase noise VCO technology and can achieve 1ps
or lower typical r ms phase jitter. This ensures that it
will easily meet clocking requirements for SDH (STM-1/
STM-4/STM-16) and SONET (OC-3/OC12/OC-48). This
device is suitable for multi-rate and multiple por t line
card applications. The ICS844004I-04 is conveniently
packaged in a small 24-pin TSSOP package.
F
EATURES
Four LVDS outputs
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
Supports the following applications: SONET/SDH, SATA,
or 10Gb Ethernet
Output frequency range: 140MHz - 170MHz,
560MHz - 680MHz
VCO range: 560MHz - 680MHz
Crystal oscillator and CLK range: 17.5MHz - 21.25MHz
RMS phase jitter @ 622.08MHz output, using a 19.44MHz
crystal (12kHz - 20MHz): 0.71ps (typical)
RMS phase jitter @ 156.25MHz output, using a 19.53125MHz
crystal (1.875MHz - 20MHz): 0.51ps (typical)
RMS phase jitter @ 155.52MHz output, using a 19.44MHz
crystal (12kHz - 5MHz): 0.75ps (typical)
Full 3.3V supply mode
-40C to 85C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
ICS844004I-04
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
nQ1
Q1
V
DD
o
Q0
nQ0
MR
F_SEL3
nc
V
DDA
F_SEL0
V
DD
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
nQ2
Q2
V
DDO
Q3
nQ3
GND
F_SEL2
INPUT_SEL
CLK
GND
XTAL_IN
XTAL_OUT
24
23
22
21
20
19
18
17
16
15
14
13
B
LOCK
D
IAGRAM
CLK
INPUT_SEL
MR
F_SEL0
F_SEL1
F_SEL2
F_SEL3
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pullup
XTAL_IN
XTAL_OUT
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844004AGI-04
www.icst.com/products/hiperclocks.html
REV. A JANUARY 26, 2006
2
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
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IN
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844004AGI-04
www.icst.com/products/hiperclocks.html
REV. A JANUARY 26, 2006
3
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
10mA
Surge Current
15mA
Package Thermal Impedance,
JA
70C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, TA = -40C
TO
85C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, TA = -40C
TO
85C
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A
m
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, TA = -40C
TO
85C
l
o
b
m
y
S
r
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t
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m
a
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V
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844004AGI-04
www.icst.com/products/hiperclocks.html
REV. A JANUARY 26, 2006
4
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, TA = -40C
TO
85C
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
r
e
t
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m
a
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P
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844004AGI-04
www.icst.com/products/hiperclocks.html
REV. A JANUARY 26, 2006
5
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
AT
622.08MH
Z
A
T
3.3V
622.08MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.71ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
OC 12 SONET Filter
Phase Noise Result by adding
OC 12 SONET Filter to raw data
Raw Phase Noise Data
dBc
Hz
N
OISE
P
O
WER
T
YPICAL
P
HASE
N
OISE
AT
155.52MH
Z
A
T
3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
155.52MHz
RMS Phase Jitter (Random)
12kHz to 5MHz = 0.75ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
10
100
1k
10k
100k
1M
10M
100M
OC3 SONET Filter
Phase Noise Result by adding
OC3 SONET Filter to raw data
Raw Phase Noise Data
dBc
Hz
N
OISE
P
O
WER
844004AGI-04
www.icst.com/products/hiperclocks.html
REV. A JANUARY 26, 2006
6
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
R
ISE
/F
ALL
T
IME
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
t
sk(o)
Qy
Qx
nQy
nQx
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
O
FFSET
V
OLTAGE
S
ETUP
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q0:Q3
nQ0:nQ3
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
RMS P
HASE
J
ITTER
SCOPE
Qx
nQx
LVDS
Power Supply
+
-
Float GND
O
UTPUT
S
KEW
100
out
out
LVDS
DC Input
V
OD
/
V
OD
V
DD
D
IFFERENTIAL
O
UTPUT
V
OLTAGE
S
ETUP
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
out
out
LVDS
DC Input
V
OS
/
V
OS
V
DD
V
DD
844004AGI-04
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REV. A JANUARY 26, 2006
7
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS844004I-04 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2
below were determined using a 19.44MHz 18pF
parallel resonant crystal and were chosen to minimize
the ppm error.
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844004I-04 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
ICS84332
XTAL_IN
XTAL_OUT
X1
18pF Parallel Cry stal
C2
22p
C1
22p
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
ICS844004I-04
844004AGI-04
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REV. A JANUARY 26, 2006
8
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
3.3V LVDS D
RIVER
T
ERMINATION
A general LVDS interface is shown in
Figure 3.
In a 100
differential transmission line environment, LVDS drivers
require a matched load termination of 100
across near
F
IGURE
3. T
YPICAL
LVDS D
RIVER
T
ERMINATION
the receiver input. For a multiple LVDS outputs buffer, if
only partial outputs are used, it is recommended to termi-
nate the unused outputs.
R1
100
3.3V
100 Ohm Differential Transmission Line
3.3V
+
-
LVDS
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
resistor can be tied from XTAL_IN to ground.
CLK I
NPUT
:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the CLK input to
ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVDS
All unused LVDS outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
844004AGI-04
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REV. A JANUARY 26, 2006
9
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
S
CHEMATIC
E
XAMPLE
Figure 4
shows a schematic example for ICS844004i-04. In this
example, the input is a 19.44MHz parallel resonant crystal with
load capacitor CL=18pF. The 22pF frequency fine tuning
capacitors are used C1 and C2. This example also shows general
logic control input handling. For decoupling capacitors, it is
recommended to have one decouple capacitor per power pin.
C6
0.1u
VCCO
C9
0.1u
RD2
1K
R2
10
+
-
Logic Control Input Examples
Zo = 50 Ohm
Zo = 50 Ohm
RD1
Not Install
C1
27pF
RU1
1K
R3
100
VCC
VCCO
C7
0.1u
VC
C
VCC
RU2
Not Install
X1
19.44MHz
C2
33pF
VCC
To Logic
Input
pins
U1
844004i-04
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
nQ
1
Q1
VD
D
O
Q0
nQ
0
MR
F
_
SEL3
NC
VD
D
A
F
_
SEL0
VD
D
F
_
SEL1
XT
AL_O
U
T
XT
AL_I
N
GN
D
CL
K
IN
P
U
T
_
S
E
L
F
_
SEL2
GN
D
nQ
3
Q3
VD
D
O
Q2
nQ
2
+
-
Set Logic
Input to
'0'
VCC
C8
0.1u
R4
100
VCCO=3.3V
Zo = 50 Ohm
Set Logic
Input to
'1'
18pF
To Logic
Input
pins
C4
0.01u
VCCA
C3
10uF
VCC=3.3V
Zo = 50 Ohm
F
IGURE
4. ICS844004I-04 S
CHEMATIC
E
XAMPLE
Each decoupling capacitor should be located as close as
possible to the power pin. The low pass filter R2, C3 and C4
should also be located as close to the VCCA pin as possible.
For LVDS driver, the unused output pairs should be terminated
with a 100
resistor across.
844004AGI-04
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REV. A JANUARY 26, 2006
10
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844004I-04.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844004I-04 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
Power (core)
MAX
= V
DD_MAX
* (I
DD_MAX
+ I
DDA_MAX
) = 3.465V * (80mA + 8mA) = 304.92mW
Power (outputs)
MAX
= V
DDO_MAX
* I
DDO_MAX
= 3.465V * 87mA = 301.45mW
Total Power
_MAX
= 304.92mW + 301.45mW = 606.37mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability
of the device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
q
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used.
Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65C/W per Table 7
below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.606W * 65C/W = 124C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
T
ABLE
7. T
HERMAL
R
ESISTANCE
JA
FOR
24-L
EAD
TSSOP, F
ORCED
C
ONVECTION
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
844004AGI-04
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REV. A JANUARY 26, 2006
11
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS844004I-04 is: 2285
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
844004AGI-04
www.icst.com/products/hiperclocks.html
REV. A JANUARY 26, 2006
12
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
24 L
EAD
TSSOP
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
S
s
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844004AGI-04
www.icst.com/products/hiperclocks.html
REV. A JANUARY 26, 2006
13
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockS and F
EMTO
C
LOCKS
are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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