Document Outline
- General Description
- Features
- Frequency Select Function Table
- Pin Assignment
- Block Diagram
- Pin Description
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVDS DC Characteristics
- Crystal Characteristics
- AC Characteristics
- Typical Phase Noise Plot
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Recommendations for Unused Input and Output Pins
- 3.3V LVDS Driver Termination
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
844008AY-16
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 1, 2006
1
Integrated
Circuit
Systems, Inc.
ICS844008-16
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
T h e I C S 8 4 4 0 0 8 - 1 6 i s a n 8 o u t p u t LV D S
Synthesizer optimized to generate PCI Express
reference clock frequencies and is a member
of the HiPerClocks
TM
family of high performance
clock solutions from ICS. Using a 25MHz
parallel resonant crystal, the following frequencies can be
generated based on F_SEL pin: 100MHz or 125MHz. The
ICS844008-16 uses ICS' 3
rd
generation low phase noise
VCO technology and can achieve <1ps typical rms phase
jitter, easily meeting PCI Express jitter requirements. The
ICS844008-16 is packaged in a 32-pin LQFP package.
F
EATURES
Eight LVDS outputs
Crystal oscillator interface
Supports the following output frequencies:
100MHz or 125MHz
VCO: 500MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.44ps (typical)
Full 3.3V supply modes
0C to 70C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q0
nQ0
V
DD
Q1
nQ1
GND
Q2
nQ2
MR
nQ4
Q4
GND
V
DD
nQ3
Q3
F_SEL
V
DDA
nPLL_SEL
V
DD
OE2
GND
XT
AL_OUT
XT
AL_IN
OE1
ICS844008-16
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
Top View
Q7
nQ7
V
DD
Q6
nQ6
GND
Q5
nQ5
1
0
Phase
Detector
VCO
500MHz
(w/25MHz
Reference)
M =
20 (fixed)
4
5
OSC
B
LOCK
D
IAGRAM
nPLL_SEL
XTAL_IN
XTAL_OUT
OE1
MR
F_SEL
OE2
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Pullup
Pullup
25MHz
Pulldown
Pullup
Pulldown
t
u
p
n
I
t
u
p
t
u
O
y
c
n
e
u
q
e
r
F
)
z
H
M
(
t
u
p
n
I
y
c
n
e
u
q
e
r
F
)
z
H
M
(
L
E
S
_
F
r
e
d
i
v
i
D
M
e
u
l
a
V
r
e
d
i
v
i
D
N
e
u
l
a
V
r
e
d
i
v
i
D
N
/
M
e
u
l
a
V
z
H
M
5
2
0
0
2
4
5
5
2
1
z
H
M
5
2
1
0
2
5
4
0
0
1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
844008AY-16
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 1, 2006
2
Integrated
Circuit
Systems, Inc.
ICS844008-16
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
C
N
I
e
c
n
a
t
i
c
a
p
a
C
t
u
p
n
I
4
F
p
R
N
W
O
D
L
L
U
P
r
o
t
s
i
s
e
R
n
w
o
d
ll
u
P
t
u
p
n
I
1
5
k
R
P
U
L
L
U
P
r
o
t
s
i
s
e
R
P
U
ll
u
P
t
u
p
n
I
1
5
k
T
ABLE
3A. OE1 F
UNCTION
T
ABLE
t
u
p
n
I
s
t
u
p
t
u
O
1
E
O
4
Q
n
:
0
Q
n
,
4
Q
:
0
Q
0
e
t
a
t
s
Z
-
i
H
n
i
s
t
u
p
t
u
o
s
e
c
a
l
P
1
n
o
i
t
a
r
e
p
o
l
a
m
r
o
N
T
ABLE
3B. OE2 F
UNCTION
T
ABLE
t
u
p
n
I
s
t
u
p
t
u
O
2
E
O
7
Q
n
:
5
Q
n
,
7
Q
:
5
Q
0
e
t
a
t
s
Z
-
i
H
n
i
s
t
u
p
t
u
o
s
e
c
a
l
P
1
n
o
i
t
a
r
e
p
o
l
a
m
r
o
N
r
e
b
m
u
N
e
m
a
N
e
p
y
T
n
o
i
t
p
i
r
c
s
e
D
2
,
1
0
Q
n
,
0
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
S
D
V
L
.
r
i
a
p
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
,
2
1
,
3
7
2
,
2
2
V
D
D
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
e
r
o
C
5
,
4
1
Q
n
,
1
Q
t
u
p
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
S
D
V
L
.
r
i
a
p
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
,
3
1
,
6
9
2
,
9
1
D
N
G
r
e
w
o
P
.
d
n
u
o
r
g
y
l
p
p
u
s
r
e
w
o
P
8
,
7
2
Q
n
,
2
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
S
D
V
L
.
r
i
a
p
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
9
L
E
S
_
F
t
u
p
n
I
p
u
ll
u
P
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
n
i
p
t
c
e
l
e
s
y
c
n
e
u
q
e
r
F
1
1
,
0
1
3
Q
n
,
3
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
S
D
V
L
.
r
i
a
p
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
5
1
,
4
1
4
Q
n
,
4
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
S
D
V
L
.
r
i
a
p
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
6
1
R
M
t
u
p
n
I
-
d
ll
u
P
n
w
o
t
e
s
e
r
e
r
a
s
r
e
d
i
v
i
d
l
a
n
r
e
t
n
i
e
h
t
,
H
G
I
H
c
i
g
o
l
n
e
h
W
.
t
e
s
e
R
r
e
t
s
a
M
H
G
I
H
e
v
i
t
c
A
x
Q
n
s
t
u
p
t
u
o
d
e
t
r
e
v
n
i
e
h
t
d
n
a
w
o
l
o
g
o
t
x
Q
s
t
u
p
t
u
o
e
u
r
t
e
h
t
g
n
i
s
u
a
c
e
r
a
s
t
u
p
t
u
o
e
h
t
d
n
a
s
r
e
d
i
v
i
d
l
a
n
r
e
t
n
i
e
h
t
,
W
O
L
c
i
g
o
l
n
e
h
W
.
h
g
i
h
o
g
o
t
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
d
e
l
b
a
n
e
8
1
,
7
1
5
Q
,
5
Q
n
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
S
D
V
L
.
r
i
a
p
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
1
2
,
0
2
6
Q
,
6
Q
n
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
S
D
V
L
.
r
i
a
p
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
4
2
,
3
2
7
Q
,
7
Q
n
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
S
D
V
L
.
r
i
a
p
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
5
2
V
A
D
D
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
g
o
l
a
n
A
6
2
L
E
S
_
L
L
P
n
t
u
p
n
I
-
d
ll
u
P
n
w
o
,
W
O
L
n
e
h
W
.
s
r
e
d
i
v
i
d
e
h
t
o
t
t
u
p
n
i
s
a
K
L
C
_
F
E
R
d
n
a
L
L
P
e
h
t
n
e
e
w
t
e
b
s
t
c
e
l
e
S
L
L
P
(
k
c
o
l
c
e
c
n
e
r
e
f
e
r
e
h
t
s
t
c
e
l
e
s
e
d
,
H
G
I
H
n
e
h
W
.
)
e
l
b
a
n
E
L
L
P
(
L
L
P
s
t
c
e
l
e
s
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
)
s
s
a
p
y
B
8
2
2
E
O
t
u
p
n
I
p
u
ll
u
P
.
s
t
u
p
t
u
o
7
Q
n
/
7
Q
:
5
Q
n
/
5
Q
r
o
f
e
l
b
a
n
e
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
1
3
,
0
3
,
T
U
O
_
L
A
T
X
N
I
_
L
A
T
X
t
u
p
n
I
,
t
u
p
t
u
o
e
h
t
s
i
T
U
O
_
L
A
T
X
.
e
c
a
f
r
e
t
n
i
l
a
t
s
y
r
c
t
n
a
n
o
s
e
r
l
e
ll
a
r
a
P
.
t
u
p
n
i
e
h
t
s
i
N
I
_
L
A
T
X
2
3
1
E
O
t
u
p
n
I
p
u
ll
u
P
.
s
t
u
p
t
u
o
4
Q
n
/
4
Q
:
0
Q
n
/
0
Q
r
o
f
e
l
b
a
n
e
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
:
E
T
O
N
p
u
ll
u
P
.
s
e
u
l
a
v
l
a
c
i
p
y
t
r
o
f
,
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
n
i
P
,
2
e
l
b
a
T
e
e
S
.
s
r
o
t
s
i
s
e
r
t
u
p
n
i
l
a
n
r
e
t
n
i
o
t
s
r
e
f
e
r
844008AY-16
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 1, 2006
3
Integrated
Circuit
Systems, Inc.
ICS844008-16
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
10mA
Surge Current
15mA
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
I
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
V
D
D
V
3
.
3
=
2
V
D
D
3
.
0
+
V
V
L
I
e
g
a
t
l
o
V
w
o
L
t
u
p
n
I
V
D
D
V
3
.
3
=
3
.
0
-
8
.
0
V
I
H
I
t
u
p
n
I
t
n
e
r
r
u
C
h
g
i
H
L
E
S
_
L
L
P
n
,
R
M
V
D
D
V
=
N
I
5
6
4
.
3
=
0
5
1
A
L
E
S
_
F
,
2
E
O
,
1
E
O
V
D
D
V
=
N
I
5
6
4
.
3
=
5
A
I
L
I
t
u
p
n
I
t
n
e
r
r
u
C
w
o
L
L
E
S
_
L
L
P
n
,
R
M
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
5
-
A
L
E
S
_
F
,
2
E
O
,
1
E
O
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
O
e
g
a
t
l
o
V
t
u
p
t
u
O
l
a
i
t
n
e
r
e
f
f
i
D
0
4
4
V
m
V
D
O
V
D
O
e
g
n
a
h
C
e
d
u
t
i
n
g
a
M
0
4
V
m
V
S
O
e
g
a
t
l
o
V
t
e
s
f
f
O
4
.
1
V
V
S
O
V
S
O
e
g
n
a
h
C
e
d
u
t
i
n
g
a
M
0
5
V
m
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
e
r
o
C
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
A
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
g
o
l
a
n
A
5
3
1
.
3
3
.
3
5
6
4
.
3
V
I
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
5
8
2
A
m
I
A
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
g
o
l
a
n
A
2
1
A
m
844008AY-16
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 1, 2006
4
Integrated
Circuit
Systems, Inc.
ICS844008-16
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
T
U
O
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
0
=
L
E
S
F
5
2
1
z
H
M
1
=
L
E
S
F
0
0
1
z
H
M
t
)
o
(
k
s
2
,
1
E
T
O
N
;
w
e
k
S
t
u
p
t
u
O
D
B
T
s
p
t
)
c
c
(
t
ij
r
e
t
t
i
J
e
l
c
y
C
-
o
t
-
e
l
c
y
C
0
4
s
p
t
)
(
t
ij
;
)
m
o
d
n
a
R
(
r
e
t
t
i
J
e
s
a
h
P
S
M
R
3
E
T
O
N
)
z
H
M
0
2
-
z
H
M
5
7
8
.
1
(
,
z
H
M
5
2
1
4
4
.
0
s
p
)
z
H
M
0
2
-
z
H
M
5
7
8
.
1
(
,
z
H
M
0
0
1
4
4
.
0
s
p
t
R
t
/
F
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
5
4
s
p
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
0
5
%
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
d
n
a
s
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
1
E
T
O
N
V
t
a
d
e
r
u
s
a
e
M
D
D
.
2
/
.
5
6
d
r
a
d
n
a
t
S
C
E
D
E
J
h
t
i
w
e
c
n
a
d
r
o
c
c
a
n
i
d
e
n
i
f
e
d
s
i
r
e
t
e
m
a
r
a
p
s
i
h
T
:
2
E
T
O
N
.
t
o
l
P
e
s
i
o
N
e
s
a
h
P
e
h
t
o
t
r
e
f
e
r
e
s
a
e
l
P
:
3
E
T
O
N
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
n
o
i
t
a
ll
i
c
s
O
f
o
e
d
o
M
l
a
t
n
e
m
a
d
n
u
F
y
c
n
e
u
q
e
r
F
4
.
2
2
5
2
2
.
7
2
z
H
M
1
E
T
O
N
;
)
m
p
p
(
n
o
il
li
M
r
e
p
s
t
r
a
P
0
0
1
m
p
p
)
R
S
E
(
e
c
n
a
t
s
i
s
e
R
s
e
i
r
e
S
t
n
e
l
a
v
i
u
q
E
0
5
e
c
n
a
t
i
c
a
p
a
C
t
n
u
h
S
7
F
p
l
e
v
e
L
e
v
i
r
D
0
0
1
W
.
l
a
t
s
y
r
c
t
n
a
n
o
s
e
r
l
e
ll
a
r
a
p
F
p
8
1
n
a
g
n
i
s
u
d
e
z
i
r
e
t
c
a
r
a
h
C
:
E
T
O
N
.
d
r
a
o
b
C
P
r
e
s
u
r
o
f
d
e
t
s
u
j
d
a
s
p
a
c
m
i
r
t
l
a
n
r
e
t
x
e
d
n
a
l
a
t
s
y
r
c
m
p
p
0
5
d
e
d
n
e
m
m
o
c
e
r
h
t
i
w
d
e
s
u
n
e
h
W
:
1
E
T
O
N
844008AY-16
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 1, 2006
5
Integrated
Circuit
Systems, Inc.
ICS844008-16
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
AT
125MH
Z
A
T
3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
125MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.44ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
1k
10k
100k
1M
10M
100M
dBc
Hz
N
OISE
P
OWER
Raw Phase Noise Data
Phase Noise Result by adding
PCI Express Filter to raw data
PCI Express Jitter Filter
844008AY-16
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 1, 2006
6
Integrated
Circuit
Systems, Inc.
ICS844008-16
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
RMS P
HASE
J
ITTER
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
t
sk(o)
Qy
Qx
nQy
nQx
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q0:Q7
nQ0:nQ7
C
YCLE
-
TO
-C
YCLE
J
ITTER
O
UTPUT
S
KEW
SCOPE
Qx
nQx
LVDS
3.3V5%
POWER SUPPLY
+
-
Float GND
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Q0:nQ7
nQ0:nQ7
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
O
FFSET
V
OLTAGE
S
ETUP
out
out
LVDS
DC Input
V
OS
/
V
OS
V
DD
D
IFFERENTIAL
O
UTPUT
V
OLTAGE
S
ETUP
100
out
out
LVDS
DC Input
V
OD
/
V
OD
V
DD
844008AY-16
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 1, 2006
7
Integrated
Circuit
Systems, Inc.
ICS844008-16
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS844008-16 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
Figure 2
below were determined using a 25MHz parallel
resonant crystal and were chosen to minimize the ppm error.
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844008-16 pro-
vides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. V
DD
and V
DDA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
C1
27p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
844008AY-16
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 1, 2006
8
Integrated
Circuit
Systems, Inc.
ICS844008-16
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
F
IGURE
3. T
YPICAL
LVDS D
RIVER
T
ERMINATION
3.3V LVDS D
RIVER
T
ERMINATION
A general LVDS interface is shown in
Figure 3.
In a 100
differential transmission line environment, LVDS drivers
require a matched load termination of 100
across near
the receiver input. For a multiple LVDS outputs buffer, if
only partial outputs are used, it is recommended to termi-
nate the unused outputs.
R1
100
3.3V
100 Ohm Differential Transmission Line
3.3V
+
-
LVDS
I
NPUTS
:
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVDS
All unused LVDS output pairs can be either left floating or
terminated with 100
across. If they are left floating, we
recommend that there is no trace attached.
844008AY-16
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 1, 2006
9
Integrated
Circuit
Systems, Inc.
ICS844008-16
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844008-16.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844008-16 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
Power (core)
MAX
= V
DD_MAX
* (I
DD_MAX
+ I
DDA_MAX
) = 3.465V * (285mA + 12mA) = 1029mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used.
Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per
Table 7 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 1.029W * 42.1C/W = 113.3C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
T
ABLE
7. T
HERMAL
R
ESISTANCE
JA
FOR
32-L
EAD
LQFP, F
ORCED
C
ONVECTION
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
844008AY-16
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 1, 2006
10
Integrated
Circuit
Systems, Inc.
ICS844008-16
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS844008-16 is: 2597
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
844008AY-16
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 1, 2006
11
Integrated
Circuit
Systems, Inc.
ICS844008-16
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EAD
LQFP
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
3
A
-
-
-
-
0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
9
0
.
0
-
-
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
.
f
e
R
0
6
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
.
f
e
R
0
6
.
5
e
C
I
S
A
B
0
8
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
0
-
-
7
c
c
c
-
-
-
-
0
1
.
0
844008AY-16
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 1, 2006
12
Integrated
Circuit
Systems, Inc.
ICS844008-16
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications.
Any other applications such as those requiring extended temperature range, high reliability or other extraordinary environmental requirements are not recommended without additional processing by
ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and may be registered
in certain jurisdictions.
r
e
b
m
u
N
r
e
d
r
O
/
t
r
a
P
g
n
i
k
r
a
M
e
g
a
k
c
a
P
g
n
i
g
a
k
c
a
P
g
n
i
p
p
i
h
S
e
r
u
t
a
r
e
p
m
e
T
6
1
-
Y
A
8
0
0
4
4
8
S
C
I
6
1
A
8
0
0
4
4
8
S
C
I
P
F
Q
L
d
a
e
L
2
3
e
b
u
t
C
0
7
o
t
C
0
T
6
1
-
Y
A
8
0
0
4
4
8
S
C
I
6
1
A
8
0
0
4
4
8
S
C
I
P
F
Q
L
d
a
e
L
2
3
l
e
e
r
&
e
p
a
t
0
0
0
1
C
0
7
o
t
C
0
F
L
6
1
-
Y
A
8
0
0
4
4
8
S
C
I
D
B
T
P
F
Q
L
"
e
e
r
F
-
d
a
e
L
"
d
a
e
L
2
3
e
b
u
t
C
0
7
o
t
C
0
T
F
L
6
1
-
Y
A
8
0
0
4
4
8
S
C
I
D
B
T
P
F
Q
L
"
e
e
r
F
-
d
a
e
L
"
d
a
e
L
2
3
l
e
e
r
&
e
p
a
t
0
0
0
1
C
0
7
o
t
C
0
.
t
n
a
il
p
m
o
c
S
H
o
R
e
r
a
d
n
a
n
o
i
t
a
r
u
g
i
f
n
o
c
e
e
r
F
-
b
P
e
h
t
e
r
a
r
e
b
m
u
n
t
r
a
p
e
h
t
o
t
x
i
f
f
u
s
"
F
L
"
n
a
h
t
i
w
d
e
r
e
d
r
o
e
r
a
t
a
h
t
s
t
r
a
p
:
E
T
O
N
PDF 
ZIP