Document Outline
- General Description
- Features
- Common Configuration Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- 3.3V Power Supply DC Characteristics
- 2.5V Power Supply DC Characteristics
- LVCMOS DC Characteristics
- 3.3V LVDS DC Characteristics
- 2.5V LVDS DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 2.5V AC Characteristics
- Parameter Measurement Information
- LVDS 3.3V Output Load AC Test Circuit Diagram
- LVDS 2.5V Output Load AC Test Circuit Diagram
- Output Rise/Fall Time Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- RMS Phase Jitter Diagram
- Offset Voltage Setup Diagram
- Differential Output Voltage Setup Diagram
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- LVDS Driver Termination
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
844021AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 29, 2005
1
Integrated
Circuit
Systems, Inc.
ICS844021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS844021I-01 is an Ethernet Clock
Generator and a member of the HiPerClocks
TM
family of high performance devices from ICS. The
ICS844021I-01 uses an 18pF parallel resonant
crystal over the range of 24.5MHz - 34MHz. For
Ether net applications, a 25MHz cr ystal is used. The
ICS844021I-01 has excellent <1ps phase jitter performance,
over the 1.875MHz - 20MHz integration range. The
ICS844021I-01 is packaged in a small 8-pin TSSOP, making
it ideal for use in systems with limited board space.
F
EATURES
(1) Differential LVDS output
Crystal oscillator interface, 18pF parallel resonant crystal
(24.5MHz - 34MHz)
Output frequency range: 122.5MHz - 170MHz
VCO range: 490MHz - 680MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.45ps (typical)
3.3V or 2.5V operating supply
-40C to 85C ambient operating temperature
HiPerClockSTM
ICS
ICS844021I-01
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
V
DDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
V
DD
Q0
nQ0
OE
8
7
6
5
B
LOCK
D
IAGRAM
OSC
Phase
Detector
VCO
490MHz - 680MHz
M = 20
(fixed)
N = 4
(fixed)
XTAL_IN
XTAL_OUT
Q0
nQ0
C
OMMON
C
ONFIGURATION
T
ABLE
- Gb E
THERNET
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SSIGNMENT
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Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844021AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 29, 2005
2
Integrated
Circuit
Systems, Inc.
ICS844021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
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844021AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 29, 2005
3
Integrated
Circuit
Systems, Inc.
ICS844021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= -40C
TO
85C
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BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, I
O
(LVDS)
Continuous Current
10mA
Surge Current
15mA
Package Thermal Impedance,
JA
101.7C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
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DD
= V
DDA
= 3.3V5%
OR
2.5V5%, T
A
= -40C
TO
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844021AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 29, 2005
4
Integrated
Circuit
Systems, Inc.
ICS844021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
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844021AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 29, 2005
5
Integrated
Circuit
Systems, Inc.
ICS844021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
R
ISE
/F
ALL
T
IME
O
FFSET
V
OLTAGE
S
ETUP
LVDS 3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
LVDS 2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
RMS P
HASE
J
ITTER
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
SCOPE
Qx
nQx
LVDS
3.3V5%
POWER SUPPLY
+
-
Float GND
Q0
nQ0
100
out
out
LVDS
DC Input
V
OD
/
V
OD
V
DD
out
out
LVDS
DC Input
V
OS
/
V
OS
V
DD
V
DD
V
DD
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
D
IFFERENTIAL
O
UTPUT
V
OLTAGE
S
ETUP
SCOPE
Qx
nQx
LVDS
2.5V5%
POWER SUPPLY
+
-
Float GND
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
844021AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 29, 2005
6
Integrated
Circuit
Systems, Inc.
ICS844021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
PRELIMINARY
A
PPLICATION
I
NFORMATION
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS844021I-01 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for dif-
ferent board layouts.
C1
33p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844021I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
and V
DDA
should
b e i n d i v i d u a l l y c o n n e c t e d t o t h e p o w e r s u p p l y
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
pin.
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V or 2.5V
.01
F
V
DD
844021AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 29, 2005
7
Integrated
Circuit
Systems, Inc.
ICS844021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
PRELIMINARY
3.3V, 2.5V LVDS D
RIVER
T
ERMINATION
A general LVDS interface is shown in
Figure 3. In a 100
differential transmission line environment, LVDS drivers
require a matched load termination of 100
across near
F
IGURE
3. T
YPICAL
LVDS D
RIVER
T
ERMINATION
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
un-used outputs.
R1
100
3.3V or 2.5V
100
Differential Transmission
VDD
+
-
LVDS
844021AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 29, 2005
8
Integrated
Circuit
Systems, Inc.
ICS844021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS844021I-01 is: 2533
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
844021AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 29, 2005
9
Integrated
Circuit
Systems, Inc.
ICS844021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
8 L
EAD
TSSOP
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
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.
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7
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0
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a
a
-
-
0
1
.
0
844021AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 29, 2005
10
Integrated
Circuit
Systems, Inc.
ICS844021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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