84426BM
www.icst.com/products/hiperclocks.html
REV. A ARPIL 2, 2003
1
Integrated
Circuit
Systems, Inc.
ICS84426
C
RYSTAL
-
TO
-LVDS
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS84426 is a Crystal-to-LVDS Clock Synthe-
sizer/Fanout Buffer and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The VCO and output frequency
can be programmed using the frequency select
pins. The low jitter characteristics of the ICS84426 make it an
ideal clock source for Serial Attached SCSI applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
6 LVDS outputs
Crystal oscillator interface
Output frequency range: 75MHz to 150MHz
Crystal input frequency: 25MHz
Cycle-to-cycle jitter: 20ps (typical)
RMS phase jitter at 150MHz, using a 25MHz crystal
(899.9KHz to 20MHz): TBD
Phase noise: TBD
Offset
Noise Power
100Hz ............... TBD
1KHz ............... TBD
10KHz ............... TBD
100KHz ............... TBD
3.3V supply voltage
0C to 70C ambient operating temperature
Industrial temperature information available upon request
HiPerClockSTM
,&6
Q0:Q5
ICS84426
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
Top View
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
1
2
3
4
5
6
7
8
9
10
11
12
V
DD
F_SEL
nc
MR
XTAL1
XTAL2
nc
V
DDA
V
DD
PLL_SEL
GND
V
DD
PLL
6
/
Feedback
Divider
OSC
6
/
Output
Divider
0
1
XTAL1
XTAL2
PLL_SEL
MR
F_SEL
nQ0:nQ5
24
23
22
21
20
19
18
17
16
15
14
13
F
UNCTION
T
ABLE
s
t
u
p
n
I
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
R
M
L
E
S
_
F
T
U
O
_
F
1
X
W
O
L
0
0
z
H
M
5
7
0
1
z
H
M
0
5
1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84426BM
www.icst.com/products/hiperclocks.html
REV. A ARPIL 2, 2003
3
Integrated
Circuit
Systems, Inc.
ICS84426
C
RYSTAL
-
TO
-LVDS
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
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m
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r
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5
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3
.
3
5
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,
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M
,
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E
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_
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2
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D
3
.
0
+
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V
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a
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w
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R
M
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V
=
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V
5
6
4
.
3
=
0
5
1
A
L
E
S
_
F
,
L
E
S
_
L
L
P
V
D
D
V
=
N
I
V
5
6
4
.
3
=
5
A
I
L
I
t
n
e
r
r
u
C
w
o
L
t
u
p
n
I
R
M
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
5
-
A
L
E
S
_
F
,
L
E
S
_
L
L
P
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
T
ABLE
3C. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
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t
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t
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e
T
m
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p
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V
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O
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t
u
p
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O
l
a
i
t
n
e
r
e
f
f
i
D
0
5
2
0
0
4
0
0
6
V
m
V
D
O
V
D
O
e
g
n
a
h
C
e
d
u
t
i
n
g
a
M
0
5
V
m
V
S
O
e
g
a
t
l
o
V
t
e
s
f
f
O
4
.
1
V
V
S
O
V
S
O
e
g
n
a
h
C
e
d
u
t
i
n
g
a
M
0
5
V
m
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
50C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= 0C
TO
70C
84426BM
www.icst.com/products/hiperclocks.html
REV. A ARPIL 2, 2003
5
Integrated
Circuit
Systems, Inc.
ICS84426
C
RYSTAL
-
TO
-LVDS
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
S
KEW
odc & t
P
ERIOD
C
YCLE
-
TO
-C
YCLE
J
ITTER
P
ERIOD
J
ITTER
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
contains 68.26% of all measurements
2
contains 95.4% of all measurements
3
contains 99.73% of all measurements
4
contains 99.99366% of all measurements
6
contains (100-1.973x10
-7
)% of all measurements
Histogram
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock Outputs
20%
80%
20%
80%
t
R
t
F
V
O D
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
nQ0:nQ5
Q0:Q5
nQ0:nQ5
Q0:Q5
tsk(o)
nQx
Qx
nQy
Qy
V
OS
/
D
VOS
S
ETUP
V
OD
/
D
VOD
S
ETUP
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
out
out
LVDS
DC Input
V
OS
/
V
OS
V
DD
100
out
out
LVDS
DC Input
V
OD
/
V
OD
V
DD
SCOPE
Qx
nQx
LVDS
3.3V5%
POWER SUPPLY
+
-
Float GND
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
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