8516FYI
www.icst.com/products/hiperclocks.html
REV. A JULY 30, 2004
1
Integrated
Circuit
Systems, Inc.
ICS8516I
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
G
ENERAL
D
ESCRIPTION
The ICS8516I is a low skew, high performance
1-to-16 Differential-to-LVDS Clock Distribution
Chip and a member of the HiPerClockSTM
family of High Performance Clock Solutions
from ICS. The ICS8516I CLK, nCLK pair can
accept any differential input levels and translates them to
3.3V LVDS output levels. Utilizing Low Voltage Differential
Signaling (LVDS), the ICS8516I provides a low power, low
noise, point-to-point solution for distributing clock signals
over controlled impedances of 100
.
Dual output enable inputs allow the ICS8516I to be used in
a 1-to-16 or 1-to-8 input/output mode. Guaranteed output
and part-to-part skew specifications make the ICS8516I ideal
for those applications demanding well defined performance
and repeatability.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
16 Differential LVDS outputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 700MHz
Translates any differential input signal (LVPECL, LVHSTL,
SSTL, DCM) to LVDS levels without external bias networks
Translates any single-ended input signal to LVDS
with resistor bias on nCLK input
Multiple output enable inputs for disabling unused
outputs in reduced fanout applications
LVDS compatible
Output skew: 65ps (maximum)
Part-to-part skew: 550ps (maximum)
Propagation delay: 2.4ns (maximum)
3.3V operating supply
-40C to 85C ambient operating temperature
HiPerClockSTM
ICS
48-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
OE1
OE2
CLK
nCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
V
DD
nQ5
Q5
nQ4
Q4
V
DD
GND
nQ3
Q3
nQ2
Q2
V
DD
V
DD
nQ10
Q10
nQ11
Q11
V
DD
GND
nQ12
Q12
nQ13
Q13
V
DD
nQ14
Q14
nQ15
Q15
GND
CLK
nCLK
GND
Q0
nQ0
Q1
nQ1
ICS8516I
Q9
nQ9
Q8
nQ8
GND
OE2
OE1
GND
nQ7
Q7
nQ6
Q6
8516FYI
www.icst.com/products/hiperclocks.html
REV. A JULY 30, 2004
4
Integrated
Circuit
Systems, Inc.
ICS8516I
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= -40C
TO
85C
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A
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
10mA
Surge Current
15mA
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Func-
tional operation of product at these conditions or any condi-
tions beyond those listed in the
DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect prod-
uct reliability.
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