Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Input Function Table
- CLK_EN Timing Diagram
- Clock Input Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- LVPECL DC Characteristics
- HSTL DC Characteristics
- AC Characteristics
- Parameter Measurement Information
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Recommendations for Unused Input and Output Pins
- Differential Clock Input Interface
- LVPECL Clock Input Interface
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- HSTL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
Integrated
Circuit
Systems, Inc.
ICS8521I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
8521BYI
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 17, 2005
1
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS8521I is a low skew, 1-to-9 Differential-
to-HSTL Fanout Buffer and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The ICS8521I has two se-
lectable clock inputs. The CLK, nCLK pair can
accept most standard differential input levels. The PCLK,
nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The clock enable is internally synchronized to eliminate runt
pulses on the outputs during asynchronous asser tion/
deassertion of the clock enable pin.
Guaranteed output skew, part-to-part skew and crossover
voltage characteristics make the ICS8521I ideal for today's
most advanced applications, such as IA64 and static RAMs.
HiPerClockSTM
ICS
F
EATURES
Nine HSTL outputs
Selectable differential CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
Maximum output frequency: 500MHz
Output skew: 25ps (typical)
Part-to-part skew: 200ps (typical)
Propagation delay: 1.3ns (typical)
V
OH
= 1.4V (maximum)
3.3V core, 1.8V output operating supply voltages
-40C to 85C ambient operating temperature
Available in both standard and lead-free RoHS
compliant packages
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5
9 1 0 1 1 1 2 1 3 1 4 1 5 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
DDO
Q3
nQ3
Q4
nQ4
Q5
nQ5
V
DDO
ICS8521I
V
DDO
Q6
nQ6
Q7
nQ7
Q8
nQ8
V
DDO
V
DDO
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
DDO
V
DD
CLK
nCLK
CLK_SEL
PCLK
nPCLK
GND
CLK_EN
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
CLK
nCLK
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
D
Q
LE
CLK_EN
CLK_SEL
0
1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
Integrated
Circuit
Systems, Inc.
ICS8521I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
8521BYI
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 17, 2005
2
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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Integrated
Circuit
Systems, Inc.
ICS8521I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
8521BYI
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 17, 2005
3
PRELIMINARY
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
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B
3
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b
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T
n
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F
IGURE
1. CLK_EN T
IMING
D
IAGRAM
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0:nQ8
Q0:Q8
Integrated
Circuit
Systems, Inc.
ICS8521I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
8521BYI
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 17, 2005
4
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
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T
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H
I
.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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6
A
m
Integrated
Circuit
Systems, Inc.
ICS8521I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
8521BYI
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 17, 2005
5
PRELIMINARY
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
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4E. HSTL DC C
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,
V
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= 1.8V0.2V, T
A
= -40C
TO
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T
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N
Integrated
Circuit
Systems, Inc.
ICS8521I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
8521BYI
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 17, 2005
6
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
P
ART
-
TO
-P
ART
S
KEW
P
ROPAGATION
D
ELAY
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
OD
t
sk(o)
nQx
Qx
nQy
Qy
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
S
KEW
3.3V C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
HSTL
Qx
nQx
V
CMR
Cross Points
V
PP
GND
CLK,
PCLK
nCLK,
nPCLK
V
DD
t
sk(pp)
nQx
Qx
nQy
Qy
PART 1
PART 2
nCLK,
nPCLK
CLK,
PCLK
nQ0:nQ8
Q0:Q8
t
PD
V
DD
GND = 0V
3.3V 5%
V
DDO
1.8V 0.2V
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
nQ0:nQ8
Q0:Q8
Integrated
Circuit
Systems, Inc.
ICS8521I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
8521BYI
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 17, 2005
7
PRELIMINARY
A
PPLICATION
I
NFORMATION
Figure 2
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
2. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
R2
1K
V
DD
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
I
NPUTS
:
CLK/nCLK I
NPUT
:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
resistor can be tied from
CLK to ground.
PCLK/nPCLK I
NPUT
:
For applications not requiring the use of a differential input,
both the PCLK and nPCLK pins can be left floating. Though
not required, but for additional protection, a 1k
resistor can
be tied from PCLK to ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
HSTL O
UTPUT
All unused LVHSTL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
Integrated
Circuit
Systems, Inc.
ICS8521I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
8521BYI
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 17, 2005
8
PRELIMINARY
F
IGURE
3C. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3B. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3D. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 3A to 3E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
3A. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S HSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 3A,
the input termination applies for ICS
HiPerClockS HSTL drivers. If you are using an HSTL driver from
another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
F
IGURE
3E. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
Integrated
Circuit
Systems, Inc.
ICS8521I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
8521BYI
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 17, 2005
9
PRELIMINARY
LVPECL C
LOCK
I
NPUT
I
NTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
SWING
and V
OH
must meet the V
PP
and V
CMR
input requirements.
Figures 4A to 4D
show inter-
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
F
IGURE
4A. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
CML D
RIVER
F
IGURE
4B. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
AN
SSTL D
RIVER
F
IGURE
4C. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
F
IGURE
4D. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
3.3V LVDS D
RIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
F
IGURE
4E. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
3.3V
R5
100 - 200
3.3V
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
Integrated
Circuit
Systems, Inc.
ICS8521I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
8521BYI
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 17, 2005
10
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8521I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8521I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 60mA = 208mW
Power (outputs)
MAX
= 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 9 * 32.8mW = 295.2mW
Total Power
_MAX
(3.465V, with all outputs switching) = 208mW + 295.2mW = 503.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used
. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.503W * 42.1C/W = 106.2C. This is well below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 6. Thermal Resistance
JA
for 32-pin LQFP, Forced Convection
Integrated
Circuit
Systems, Inc.
ICS8521I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
8521BYI
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 17, 2005
11
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVHSTL output driver circuit and termination are shown in
Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MIN
/R
L
) * (V
DDO_MAX
- V
OH_MIN
)
Pd_L = (V
OL_MAX
/R
L
) * (V
DDO_MAX
- V
OL_MAX
)
Pd_H = (1.0V/50
) * (2V - 1.0V) = 20mW
Pd_L = (0.4V/50
) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
F
IGURE
5. HSTL D
RIVER
C
IRCUIT
AND
T
ERMINATION
V
DDO
V
OUT
RL
50
Q1
Integrated
Circuit
Systems, Inc.
ICS8521I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
8521BYI
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 17, 2005
12
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8521I is: 944
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Integrated
Circuit
Systems, Inc.
ICS8521I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
8521BYI
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 17, 2005
13
PRELIMINARY
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EAD
LQFP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
3
A
-
-
-
-
0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
9
0
.
0
-
-
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
.
f
e
R
0
6
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
.
f
e
R
0
6
.
5
e
C
I
S
A
B
0
8
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
0
-
-
7
c
c
c
-
-
-
-
0
1
.
0
Reference Document: JEDEC Publication 95, MS-026
Integrated
Circuit
Systems, Inc.
ICS8521I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
8521BYI
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 17, 2005
14
PRELIMINARY
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no
responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or
licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high
reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change
any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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