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8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
1
Integrated
Circuit
Systems, Inc.
ICS8523I-03
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS8523I-03
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm body package
G Package
Top View
GND
CLK_EN
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
nc
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
DDO
Q1
nQ1
Q2
nQ2
V
DDO
Q3
nQ3
G
ENERAL
D
ESCRIPTION
The ICS8523I-03 is a low skew, high perfor-
mance 1-to-4 Differential-to-LVHSTL fanout buffer
and a member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. The
ICS8523I-03 has two selectable clock inputs.
The input pairs can accept most standard differential input
levels. The clock enable is inter nally synchronized to
eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8523I-03 ideal for those applications demand-
ing well defined performance and repeatability.
F
EATURES
4 differential LVHSTL compatible outputs
Selectable differential CLK0, nCLK0 and CLK1, nCLK1
clock inputs
Clock input pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 650MHz
Translates any single-ended input signal to LVHSTL
levels with resistor bias on nCLK input
Output skew: 50ps (maximum)
Part-to-part skew: 400ps (maximum)
Propagation delay: 1.2ns (typical)
V
OH
= 1V (maximum)
3.3V core, 1.8V output operating supply
Lead-Free package available
-40C to 85C ambient operating temperature
HiPerClockSTM
ICS
CLK0
nCLK0
CLK1
nCLK1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
0
1
CLK_EN
CLK_SEL
D
Q
LE
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
2
Integrated
Circuit
Systems, Inc.
ICS8523I-03
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
3
Integrated
Circuit
Systems, Inc.
ICS8523I-03
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
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8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
4
Integrated
Circuit
Systems, Inc.
ICS8523I-03
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
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m
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C
:
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E
T
O
N
H
I
.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
5
Integrated
Circuit
Systems, Inc.
ICS8523I-03
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
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4D. LVHSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
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8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
6
Integrated
Circuit
Systems, Inc.
ICS8523I-03
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
P
ART
-
TO
-P
ART
S
KEW
P
ROPAGATION
D
ELAY
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
OD
t
sk(o)
nQx
Qx
nQy
Qy
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
S
KEW
3.3V C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
LVHSTL
Qx
nQx
V
CMR
Cross Points
V
PP
GND
CLK0,
CLK1
nCLK0,
nCLK1
V
DD
tsk(pp)
nQx
Qx
nQy
Qy
PART 1
PART 2
nCLK0,
nCLK1
CLK0,
CLK1
nQ0:nQ3
Q0:Q3
t
PD
V
DD
GND = 0V
3.3V 5%
V
DDO
1.8V 0.2V
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
nQ0:nQ3
Q0:Q3
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
7
Integrated
Circuit
Systems, Inc.
ICS8523I-03
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
2. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLKx
nCLKx
VDD
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
8
Integrated
Circuit
Systems, Inc.
ICS8523I-03
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
F
IGURE
3C. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3B. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3D. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 3A to 3E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
3A. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 4A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
F
IGURE
3E. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
9
Integrated
Circuit
Systems, Inc.
ICS8523I-03
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
Zo = 50
+
-
C2
0.1u
Zo = 50
C1
0.1u
Zo = 50
R5
50
R2
50
R8
50
+
-
R1
50
R3
50
R12
1K
+
-
R4
50
R9
50
Zo = 50 Ohm
3.3V
Zo = 50 Ohm
R7
50
R10
50
Zo = 50
R6
50
3.3V
+
-
1.8V
Zo = 50
LVHSTL Driver
C3
0.1u
1.8V
1.8V
Zo = 50
Zo = 50
U1
ICS8523-03
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
GND
CLK_EN
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
NC
NC
VDD
nQ3
Q3
VDDO
nQ2
Q2
nQ1
Q0
nQ0
VDDO
Q1
1.8V
Zo = 50
R11
1K
S
CHEMATIC
E
XAMPLE
This application note provides general design guide using
ICS8523I-03 LVHSTL buffer. Figure 3 shows a schematic ex-
ample of the ICS8523I-03 LVHSTL Clock buffer. In this example,
F
IGURE
4. E
XAMPLE
ICS8523I-03 LVHSTL C
LOCK
O
UTPUT
B
UFFER
S
CHEMATIC
the input is driven by an LVHSTL driver. CLK_EN is set at logic
low to select CLK0/nCLK0 input.
8523AGI-03
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REV. A OCTOBER 5, 2004
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Integrated
Circuit
Systems, Inc.
ICS8523I-03
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8523I-03.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8523I-03 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 55mA = 190mW
Power (outputs)
MAX
= 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 32.8mW = 131mW
Total Power
_MAX
(3.465V, with all outputs switching) = 190mW + 131mW = 321mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.321W * 66.6C/W = 106.4C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
6. T
HERMAL
R
ESISTANCE


JA
FOR
20-
PIN
TSSOP, F
ORCED
C
ONVECTION
8523AGI-03
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OW
S
KEW
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TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVHSTL output driver circuit and termination are shown in
Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MAX
/R
L
) * (V
DDO_MAX
- V
OH_MAX
)
Pd_L = (V
OL_MAX
/R
L
) * (V
DDO_MAX
- V
OL_MAX
)
Pd_H = (1V/50
) * (2V - 1V) = 20mW
Pd_L = (0.4V/50
) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
F
IGURE
5. LVHSTL D
RIVER
C
IRCUIT
AND
T
ERMINATION
V
DDO
V
OUT
RL
50
Q1
8523AGI-03
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REV. A OCTOBER 5, 2004
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ICS8523I-03
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8523I-03 is: 472
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
20 L
EAD
TSSOP


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8523AGI-03
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REV. A OCTOBER 5, 2004
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Systems, Inc.
ICS8523I-03
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OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
20 L
EAD
TSSOP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-153
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8523AGI-03
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REV. A OCTOBER 5, 2004
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Systems, Inc.
ICS8523I-03
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OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional
processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
8523AGI-03
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REV. A OCTOBER 5, 2004
15
Integrated
Circuit
Systems, Inc.
ICS8523I-03
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
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