8523BG
www.icst.com/products/hiperclocks.html
REV. B JULY 31, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS8523
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm body package
G Package
Top View
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
DDO
Q1
nQ1
Q2
nQ2
V
DDO
Q3
nQ3
CLK
nCLK
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
0
1
CLK_EN
CLK_SEL
D
Q
LE
G
ENERAL
D
ESCRIPTION
The ICS8523 is a low skew, high perfor-
mance 1-to-4 Differential-to-LVHSTL fanout buffer
and a member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. The
ICS8523 has two selectable clock inputs. The
CLK, nCLK pair can accept most standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or
SSTL input levels. The clock enable is internally synchronized
to eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8523 ideal for those applications demanding
well defined performance and repeatability.
F
EATURES
4 differential 1.8V LVHSTL outputs
Selectable CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
Maximum output frequency up to 650MHz
Translates any single-ended input signal to 1.8V LVHSTL
levels with resistor bias on nCLK input
Output skew: 30ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 1.6ns (maximum)
3.3V core, 1.8V output operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
HiPerClockSTM
,&6
8523BG
www.icst.com/products/hiperclocks.html
REV. B JULY 31, 2001
4
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DDx
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
73.2C/W
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
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