www.docs.chipfind.ru
853001AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 29, 2005
1
Integrated
Circuit
Systems, Inc.
ICS853001
1:1, D
IFFERENTIAL
LVPECL-
TO
-
2.5V, 3.3V, 5V LVPECL/ECL B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS853001 is a 1:1 Differential LVPECL-
to-LVPE C L B u f fe r a n d a m e m b e r o f t h e
HiPerClock S TM
family of High Perfor mance
Clock Solutions from ICS. The ICS853 001
may be used to regenerate LVPECL clocks which
may have been attenuated, across a long trace, or may also
be used as a differential-to-LVPECL translator. The differen-
tial input can accept the following differential input types:
LVPECL, LVDS and CML. The device also has an output en-
able pin for debug/test purposes. When the output is disabled,
it drives differential LOW (Q = LOW, nQ = HIGH). The
ICS853001 is packaged in either a 3mm x 3mm 8-pin TSSOP
or 3.9mm x 4.9mm 8-pin SOIC, making it ideal for use on
space-constrained boards.
F
EATURES
1:1 Differential LVPECL-to-LVPECL / ECL buffer
1 LVPECL clock output pair
1 Differential LVPECL PCLK, nPCLK input pair
PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML
Maximum output frequency: >2.5GHz
Part-to-part skew: 100ps (maximum)
Propagation delay: 500ps (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 5.25V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -5.25V to -2.375V
-40C to 85C ambient operating temperature
Lead-Free package RoHS compliant
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS853001
8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
Top View
V
CC
Q
nQ
V
EE
1
2
3
4
HiPerClockSTM
ICS
OE
PCLK
nPCLK
V
BB
8
7
6
5
Q
nQ
OE
PCLK
nPCLK
V
BB
D Q
LE
ICS853001
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
853001AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 29, 2005
2
Integrated
Circuit
Systems, Inc.
ICS853001
1:1, D
IFFERENTIAL
LVPECL-
TO
-
2.5V, 3.3V, 5V LVPECL/ECL B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
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K
853001AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 29, 2005
3
Integrated
Circuit
Systems, Inc.
ICS853001
1:1, D
IFFERENTIAL
LVPECL-
TO
-
2.5V, 3.3V, 5V LVPECL/ECL B
UFFER
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
5.25V; V
EE
= 0V, T
A
= -40C
TO
85C
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A
BSOLUTE
M
AXIMUM
R
ATINGS
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Supply Voltage, V
CC
6V (LVPECL mode, V
EE
= 0)
Negative Supply Voltage, V
EE
-6V (ECL mode, V
CC
= 0)
Inputs, V
I
(LVPECL mode)
-0.5V to V
CC
+ 0.5 V
Inputs, V
I
(ECL mode)
0.5V to V
EE
- 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
V
BB
Sink/Source, I
BB
0.5mA
Operating Temperature Range, TA -40C to +85C
Storage Temperature, T
STG
-65C to 150C
Package Thermal Impedance,
JA
8 Lead TSSOP
101.7C/W (0 m/s)
8 Lead SOIC
112.7C/W (0 lfpm)
(Junction-to-Ambient)
T
ABLE
3B. LVCMOS DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
5.25V; V
EE
= 0V, T
A
= -40C
TO
85C
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,
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CC
= 0V; V
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TO
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A
= -40C
TO
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A
853001AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 29, 2005
4
Integrated
Circuit
Systems, Inc.
ICS853001
1:1, D
IFFERENTIAL
LVPECL-
TO
-
2.5V, 3.3V, 5V LVPECL/ECL B
UFFER
T
ABLE
4. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.25V
TO
-2.375V
OR
V
CC
= 2.375
TO
5.25V; V
EE
= 0V, T
A
= -40C
TO
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3D. LVPECL DC C
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853001AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 29, 2005
5
Integrated
Circuit
Systems, Inc.
ICS853001
1:1, D
IFFERENTIAL
LVPECL-
TO
-
2.5V, 3.3V, 5V LVPECL/ECL B
UFFER
A
DDITIVE
P
HASE
J
ITTER
Additive Phase Jitter, RMS
@ 155.52MHz (12KHz to 20MHz)
= 0.03ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dBc/H
Z
Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVCMOS/ECL DC Characteristics
- LVPECL DC Characteristics
- AC Characteristics
- Parameter Measurement Information
- Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Part-to-Part Skew Diagram
- Propagation Delay Diagram
- Output Rise/Fall Time Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended LVCMOS Levels
- Wiring the Differential Input to Accept Single Ended LVPECL Level
- Termination for 2.5V LVPECL Output
- Termination for 3.3V LVPECL Output
- Termination for 5V LVPECL Output
- LVPECL Clock Input Interface
- Application Schematic Example
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance for 8-Pin TSSOP
- Thermal Resistance for 8-Pin SOIC
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline for 8 Lead TSSOP
- Package Dimensions for 8 Lead TSSOP
- Package Outline for 8 Lead SOIC
- Package Dimensions for 8 Lead SOIC
- Ordering Information
PDF 
ZIP