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Электронный компонент: ICS853014BGT

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853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
1
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS853014 is a low skew, high performance
1-to-5, 2.5V/3.3V Differential-to-LVPECL/ECL
Fanout Buffer and a member of the HiPerClockSTM
family of High Performance Clock Solutions
from ICS. The ICS853014 has two selectable
clock inputs.
Guaranteed output and par t-to-part skew characteristics
m a k e t h e I C S 8 5 3 0 1 4 i d e a l f o r t h o s e a p p l i c a t i o n s
demanding well defined performance and repeatability.
F
EATURES
5 differential LVPECL/ECL outputs
2 selectable differential LVPECL clock inputs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: > 2GHz
Output skew: 13ps (typical)
Part-to-part skew: 60ps (typical)
Propagation delay: 460ps (typical)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.8V to -2.375V
-40C to 85C ambient operating temperature
Lead-Free package fully RoHS compliant
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
nEN
V
CC
nPCLK1
PCLK1
V
BB
nPCLK0
PCLK0
CLK_SEL
V
EE
HiPerClockSTM
ICS
ICS853014
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
PCLK0
nPCLK0
PCLK1
nPCLK1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
0
1
nEN
CLK_SEL
D
Q
LE
0
1
V
BB
853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
2
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
3
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
T
ABLE
3A. C
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I
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T
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F
IGURE
1. nEN T
IMING
D
IAGRAM
Enabled
Disabled
nPCLK0, nPCLK1
PCLK0, PCLK1
nEN
nQ0:nQ4
Q0:Q4
853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
4
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
T
ABLE
4B. DC C
HARACTERISTICS
,
V
CC
= 3.3V, V
EE
= 0V
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V; V
EE
= 0V
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S
r
e
w
o
P
5
7
A
m
A
BSOLUTE
M
AXIMUM
R
ATINGS
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Supply Voltage, V
CC
4.6V (LVPECL mode, V
EE
= 0)
Negative Supply Voltage, V
EE
-4.6V (ECL mode, V
CC
= 0)
Inputs, V
I
(LVPECL mode)
-0.5V to V
CC
+ 0.5V
Inputs, V
I
(ECL mode)
0.5V to V
EE
- 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
V
BB
Sing/Source, I
BB
0.5mA
Operating Temperature Range, TA -40C to +85C
Storage Temperature, T
STG
-65C to 150C
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
(Junction-to-Ambient)
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3
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0
+
853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
5
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.5V; V
EE
= 0V
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C
C
.
V
3
.
0
+
853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
6
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
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A
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r
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N
853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
7
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
S
ETUP
AND
H
OLD
T
IME
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ROPAGATION
D
ELAY
V
CMR
Cross Points
V
PP
V
EE
nPCLK0,
nPCLK1
V
CC
PCLK0,
PCLK1
SCOPE
Qx
nQx
LVPECL
2V
-0.375V to -1.8V
tsk(pp)
tsk(o)
nQx
Qx
nQy
Qy
PART 1
PART 2
nQx
Qx
nQy
Qy
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
t
PD
nPCLK0,
nPCLK1
Q0:Q4
nQ0:nQ4
PCLK0,
PCLK1
t
HOLD
t
SET-UP
V
EE
V
CC
nPCLK0,
nPCLK1
PCLK0,
PCLK1
nEN
853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
8
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
3.3V LVPECL O
UTPUTS
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
Figure 2 shows an example of the differential input that can be
wired to accept single ended levels. The reference voltage level
V
BB
generated from the device is connected to the negative input.
F
IGURE
2. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
CLK_IN
C1
0.1uF
VDD(or VCC)
+
-
VBB
The C1 capacitor should be located as close as possible to the
input pin.
853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
9
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very close to
ground level. The R3 in Figure 4B can be eliminated and the
termination is shown in
Figure 4C.
F
IGURE
4C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
F
IGURE
4B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
F
IGURE
4A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
Zo = 50 Ohm
R1
250
+
-
2.5V
2,5V LVPECL
Driv er
R4
62.5
R3
250
Zo = 50 Ohm
2.5V
VCC=2.5V
R1
50
R3
18
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
VCC=2.5V
2.5V
R2
50
2,5V LVPECL
Driv er
VCC=2.5V
R1
50
R2
50
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
+
-
853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
10
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
LVPECL C
LOCK
I
NPUT
I
NTERFACE
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other
differential signals. Both V
SWING
and V
OH
must meet the V
PP
and
V
CMR
input requirements.
Figures 5A to 5E show interface
examples for the HiPerClockS PCLKx/nPCLKx input driven
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
F
IGURE
5A. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
CML D
RIVER
F
IGURE
5B. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
AN
SSTL D
RIVER
F
IGURE
5C. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
F
IGURE
5D. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVDS D
RIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
F
IGURE
5E. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
3.3V
R5
100 - 200
3.3V
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
PC L K/n PCL K
853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
11
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
S
CHEMATIC
E
XAMPLE
This application note provides general design guide using
ICS853014 LVPECL buffer.
Figure 6
shows a schematic example
of the ICS853014 LVPECL clock buffer. In this example, the in-
put is driven by an LVPECL driver. CLK_SEL is set at logic high
to select PCLK1/nPCLK1 input.
F
IGURE
6. E
XAMPLE
ICS853014 LVPECL C
LOCK
O
UTPUT
B
UFFER
S
CHEMATIC
R5
50
Zo = 50
R10
50
C5
0.1u
R4
50
C2
0.1u
R1
50
Zo = 50
C4
0.1u
+
-
C1
0.1u
+
-
R7
50
LVPECL Driv er
C3
0.1u
Zo = 50
Zo = 50
R12
1K
U1
ICS853014
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
VEE
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
VCC
nEN
VCC
nPCLK1
R11
1K
R6
50
3.3V
3.3V
R2
50
Zo = 50
3.3V
R9
50
R3
50
Zo = 50
3.3V
853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
12
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853014.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853014 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.8V * 75mA = 285mW
Power (outputs)
MAX
= 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30.94mW = 154.7mW
Total Power
_MAX
(3.8V, with all outputs switching) = 285mW + 154.7mW = 439.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used
. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.440W * 66.6C/W = 114.3C. This is well below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
6. T
HERMAL
R
ESISTANCE


JA
FOR
20-
PIN
TSSOP, F
ORCED
C
ONVECTION
853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
13
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in
Figure 7.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
0.935V
(V
CC_MAX
- V
OH_MAX
) = 0.935V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.67V
(V
CC_MAX
- V
OL_MAX
) = 1.67V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.935V)/50
] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.67V)/50
] * 1.67V = 11.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
F
IGURE
7. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
VOUT
Q1
VCC - 2V
RL
50
VCC
853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
14
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS853014 is: 373
Pin compatible with MC100LVEP14 and SY100EP14U
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
20 L
EAD
TSSOP


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
15
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
20 L
EAD
TSSOP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
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853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
16
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
ANOUT
B
UFFER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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may be registered in certain jurisdictions.
853014BG
www.icst.com/products/hiperclocks.html
REV. C MAY 13, 2005
17
Integrated
Circuit
Systems, Inc.
ICS853014
L
OW
S
KEW
, 1-
TO
-5
2.5V/3.3V D
IFFERENTIAL
-
TO
-LVPECL/ECL F
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