Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- 3.3V LVPECL DC Characteristics
- 5V LVPECL DC Characteristics
- ECL DC Characteristics
- AC Characteristics
- Parameter Measurement Information
- Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Output Rise/Fall Time Diagram
- Propagation Delay Diagram
- Duty Cycle Skew Diagram
- Application Information
- Wiring the Input to Accept Single Ended LVPECL Levels
- Termination for 3.3V LVPECL Outputs
- Termination for 5V LVPECL Outputs
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance for 8 Pin SOIC
- Thermal Resistance for 8 Pin TSSOP
- Calculations & Equations
- LVPECL Driver Circuit & Termination
- Reliability Information
- Transistor Count
- Package Outline for 8 Lead SOIC
- Package Dimensions for 8 Lead SOIC
- Package Outline for 8 Lead TSSOP
- Package Dimensions for 8 Lead TSSOP
- Ordering Information
853016AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
1
Integrated
Circuit
Systems, Inc.
ICS853016
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V, 5V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS853016 is a low skew, high perfor-
mance 1-to-2 Differential-to-3.3V, 5V LVPECL/
ECL Fanout Buffer and a member of the
HiPerClockSTM
family of High Perfor mance
Clock Solutions from ICS. The ICS853016
is characterized to operate from either a 3.3V or a 5V
power supply. Guaranteed duty cycle skew character-
istic makes the ICS853016 ideal for those clock distri-
bution applications demanding well defined perfor-
mance and repeatability.
F
EATURES
(1) Differential 3.3V, 5V LVPECL / ECL output pair and
(1) Single-ended 3.3V, 5V LVPECL / ECL output
(1) Differential D, nD input pair
D, nD pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Output frequency: >3GHz (typical)
Translates any single ended input signal to 3.3V to 5V
LVPECL levels with resistor bias on nD input
Duty cycle skew: 10ps (typical)
Propagation delay: 400ps (typical)
LVPECL mode operating voltage supply range:
V
CC
= 3.0V to 5.5V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -5.5V to -3.0V
-40C to 85C ambient operating temperature
Pin compatible with MC100EP16VCD and MC100EP16VCDT
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS853016
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
nQ
D
V
BB
/nD
nEN
1
2
3
4
HiPerClockSTM
ICS
Vcc
Q
HG
nQ
HG
V
EE
8
7
6
5
ICS853016
8-Lead TSSOP, 118mil
3mm x 3mm x 0.95mm package body
G Package
Top View
LEN
Q
LATCH
D
OE
V
BB
nQ
D
V
BB
/nD
nEN
V
CC
Q
HG
nQ
HG
V
EE
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853016AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
2
Integrated
Circuit
Systems, Inc.
ICS853016
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V, 5V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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853016AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
3
Integrated
Circuit
Systems, Inc.
ICS853016
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V, 5V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.0V
TO
5.5V; V
EE
= 0V
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BSOLUTE
M
AXIMUM
R
ATINGS
T
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HARACTERISTICS
,
V
CC
= 3.3V; V
EE
= 0V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Supply Voltage, V
CC
6V (LVPECL mode, V
EE
= 0)
Negative Supply Voltage, V
EE
-6V (ECL mode, V
CC
= 0)
Inputs, V
I
(LVPECL mode)
-0.5V to V
CC
+ 0.5V
Inputs, V
I
(ECL mode)
0.5V to V
EE
- 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
V
BB
Sink/Source, I
BB
0.5mA
Operating Temperature Range, TA -40C to +85C
Storage Temperature, T
STG
-65C to 150C
Package Thermal Impedance,
JA
112.7C/W (0 lfpm)
(Junction-to-Ambient) for 8 Lead SOIC
Package Thermal Impedance,
JA
101.7C/W (0 m/s)
(Junction-to-Ambient) for 8 Lead TSSOP
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853016AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
4
Integrated
Circuit
Systems, Inc.
ICS853016
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V, 5V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
3D. ECL DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.5V
TO
-3.0V
T
ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 5.0V; V
EE
= 0V
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853016AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
5
Integrated
Circuit
Systems, Inc.
ICS853016
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V, 5V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
4. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.5V
TO
-3.0V
OR
V
CC
= 3.0V
TO
5.5V; V
EE
= 0V
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853016AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
6
Integrated
Circuit
Systems, Inc.
ICS853016
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V, 5V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ROPAGATION
D
ELAY
V
CMR
Cross Points
V
PP
V
EE
nQ
HG
V
CC
Q
HG
SCOPE
Qx
nQx
LVPECL
2V
-3.5V to -1.0V
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
tp
LH
nQ
Q
HG
nQ
HG
D
V
CC
V
EE
n D
tsk(odc)
D
UTY
C
YCLE
S
KEW
Q
HG
nQ
HG
Q
HG
nQ
HG
Part 1
Part 2
853016AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
7
Integrated
Circuit
Systems, Inc.
ICS853016
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V, 5V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
A
PPLICATION
I
NFORMATION
F
IGURE
1. S
INGLE
E
NDED
LVPECL S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
Figure 1 shows an example of the input that can be wired to
accept single ended LVPECL levels.
W
IRING
THE
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
LVPECL L
EVELS
VCC
C1
0.1u
D
VBB/nD
CLK_IN
853016AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
8
Integrated
Circuit
Systems, Inc.
ICS853016
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V, 5V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
3.3V LVPECL O
UTPUTS
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
T
ERMINATION
FOR
5V LVPECL O
UTPUT
This section shows examples of 5V LVPECL output termina-
tion.
Figure 3A shows standard termination for 5V LVPECL. The
termination requires matched load of 50
resistors pull down to
Zo = 50 Ohm
R2
50
Zo = 50 Ohm
5V
3V
PECL
+
-
R1
50
5V
PECL
R4
84
5V
Zo = 50 Ohm
R3
84
R2
125
5V
PECL
PECL
+
-
Zo = 50 Ohm
R1
125
F
IGURE
3A. S
TANDARD
5V PECL O
UTPUT
T
ERMINATION
F
IGURE
3B. 5V PECL O
UTPUT
T
ERMINATION
E
XAMPLE
V
CC
- 2V = 3V at the receiver. Figure 3B shows Thevenin equiva-
lence of Figure 3A. In actual application where the 3V DC power
supply is not available, this approached is normally used.
853016AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
9
Integrated
Circuit
Systems, Inc.
ICS853016
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V, 5V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853016.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853016 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 5.5V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 5.5V * 30mA = 165mW
Power (outputs)
MAX
= 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW
Total Power
_MAX
(3.8V, with all outputs switching) = 165mW + 61.88mW = 226.88mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5A below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.227W * 103.3C/W = 108.4C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
153.3C/W
128.5C/W
115.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7C/W
103.3C/W
97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
5A. T
HERMAL
R
ESISTANCE
JA
FOR
8-
PIN
SOIC, F
ORCED
C
ONVECTION
T
ABLE
5B. T
HERMAL
R
ESISTANCE
JA
FOR
8-
PIN
TSSOP, F
ORCED
C
ONVECTION
JA
by Velocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
853016AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
10
Integrated
Circuit
Systems, Inc.
ICS853016
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V, 5V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
0.935V
(V
CC_MAX
- V
OH_MAX
) = 0.935V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.67V
(V
CCO_MAX
- V
OL_MAX
) = 1.67V
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC _MAX
- V
OH_MAX
) =
[(2V - 0.935V)/50
] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.67V)/50
] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
Figure 4. LVPECL Driver Circuit and Termination
VOUT
Q1
VCC - 2V
RL
50
VCC
853016AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
11
Integrated
Circuit
Systems, Inc.
ICS853016
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V, 5V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS853016 is: 163
T
ABLE
6A.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
SOIC
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
153.3C/W
128.5C/W
115.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7C/W
103.3C/W
97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
6B.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
853016AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
12
Integrated
Circuit
Systems, Inc.
ICS853016
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V, 5V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
8 L
EAD
TSSOP
T
ABLE
7B. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-187
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ABLE
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ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-012
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853016AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
13
Integrated
Circuit
Systems, Inc.
ICS853016
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V, 5V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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