Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Input Function Table
- Absolute Maximum Ratings
- 2.5V DC Characteristics
- 3.3V DC Characteristics
- 5.5V DC Characteristics
- ECL DC Characteristics
- AC Characteristics
- Additive Phase Jitter
- Parameter Measurement Information
- Output Load AC Test Circuit Diagram
- Propagation Delay Diagram
- Output Rise/Fall Time Diagram
- Application Information
- Termination for 2.5V LVPECL Output
- Termination for 3.5V LVPECL Output
- Termination for 5V LVPECL Output
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline for 8 Lead TSSOP
- Package Dimensions for 8 Lead TSSOP
- Package Outline for 8 Lead SOIC
- Package Dimensions for 8 Lead SOIC
- Ordering Information
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
1
Integrated
Circuit
Systems, Inc.
ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS853052 is a Dual LVCMOS / LVTTL-to-
Differential 2.5V, 3.3V, 5V LVPECL Multiplexer
and a member of the HiPerClocksTM family of High
Performance Clocks Solutions from ICS. The
ICS853052 has two selectable single ended
clock inputs. The single ended clock input accepts LVCMOS
or LVTTL input levels and translates them to 2.5V, 3.3V or 5V
LVPECL levels. The small outline 8-pin TSSOP or 8-pin SOIC
packages make this device ideal for applications where space,
high performance and low power are important.
F
EATURES
1 differential 2.5V, 3.3V or 5V LVPECL output
2 selectable LVCMOS/LVTTL clock inputs
Output frequency: TBD
Additive phase jitter, RMS: 0.06ps (typical)
Propagation Delay: 370ps (typical)
2.5V, 3.3V or 5V operating supply voltage
(operating range 2.375V to 5.5V)
-40C to 85C ambient operating temperature
Pin compatible with MC100EP58
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS853052
8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
Top View
8-Lead SOIC, 150 mil
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
nc
D a
D b
SEL
1
2
3
4
nQ
Q
D a
HiPerClockSTM
ICS
V
CC
Q
nQ
V
EE
8
7
6
5
1
0
D b
SEL
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
2
Integrated
Circuit
Systems, Inc.
ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
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853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
3
Integrated
Circuit
Systems, Inc.
ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Supply Voltage, V
CC
6V (LVPECL mode, V
EE
= 0)
Negative Supply Voltage, V
EE
-6V (ECL mode, V
CC
= 0)
Inputs, V
I
(LVPECL mode)
-0.5V to V
CC
+ 0.5 V
Inputs, V
I
(ECL mode)
0.5V to V
EE
- 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Operating Temperature Range, TA -40C to +85C
Storage Temperature, T
STG
-65C to 150C
Package Thermal Impedance,
JA
101.7C/W (0 m/s) TSSOP
(Junction-to-Ambient)
112.7C/W (0 lfpm) SOIC
T
ABLE
4A. DC C
HARACTERISTICS
,
V
CC
= 2.5V; V
EE
= 0V
T
ABLE
4B. DC C
HARACTERISTICS
,
V
CC
= 3.3V; V
EE
= 0V
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853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
4
Integrated
Circuit
Systems, Inc.
ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
PRELIMINARY
T
ABLE
4D. ECL DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.5V
TO
-2.375V
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.5V
TO
-2.375V
OR
V
CC
= 2.375V
TO
5.5V; V
EE
= 0V
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o
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C
C
.
V
2
-
T
ABLE
4C. DC C
HARACTERISTICS
,
V
CC
= 5V; V
EE
= 0V
853052AG
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REV. A JULY 1, 2004
5
Integrated
Circuit
Systems, Inc.
ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
PRELIMINARY
A
DDITIVE
P
HASE
J
ITTER
Input/Output Additive Phase Jitter
@ 155.52MHz (12KHz to 20MHz)
= 0.06ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dBc/H
Z
853052AG
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REV. A JULY 1, 2004
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Integrated
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ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
P
ROPAGATION
D
ELAY
O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
t
PD
V
EE
Da Db
Q
nQ
-3.5V to -0.375V
V
CC
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
853052AG
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REV. A JULY 1, 2004
7
Integrated
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Systems, Inc.
ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
PRELIMINARY
A
PPLICATION
I
NFORMATION
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 1A and Figure 1B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very close to
ground level. The R3 in Figure 1B can be eliminated and the
termination is shown in
Figure 1C.
F
IGURE
1C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
F
IGURE
1B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
F
IGURE
1A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
Zo = 50 Ohm
R1
250
+
-
2.5V
2,5V LVPECL
Driv er
R4
62.5
R3
250
Zo = 50 Ohm
2.5V
VCC=2.5V
R1
50
R3
18
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
VCC=2.5V
2.5V
R2
50
2,5V LVPECL
Driv er
VCC=2.5V
R1
50
R2
50
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
+
-
853052AG
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REV. A JULY 1, 2004
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Integrated
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Systems, Inc.
ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
PRELIMINARY
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
3.3V LVPECL O
UTPUTS
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
T
ERMINATION
FOR
5V LVPECL O
UTPUT
This section shows examples of 5V LVPECL output termina-
tion.
Figure 3A shows standard termination for 5V LVPECL. The
termination requires matched load of 50
resistors pull down to
Zo = 50 Ohm
R2
50
Zo = 50 Ohm
5V
3V
PECL
+
-
R1
50
5V
PECL
R4
84
5V
Zo = 50 Ohm
R3
84
R2
125
5V
PECL
PECL
+
-
Zo = 50 Ohm
R1
125
F
IGURE
3A. S
TANDARD
5V PECL O
UTPUT
T
ERMINATION
F
IGURE
3B. 5V PECL O
UTPUT
T
ERMINATION
E
XAMPLE
V
CC
- 2V = 3V at the receiver.
Figure 3B shows Thevenin equiva-
lence of Figure 3A. In actual application where the 3V DC power
supply is not available, this approached is normally used.
853052AG
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REV. A JULY 1, 2004
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Integrated
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Systems, Inc.
ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853052.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853052 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 5.5V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 5.5V * 21mA = 115.5mW
Power (outputs)
MAX
= 30.94mW/Loaded Output pair
Total Power
_MAX
(5.5V, with all outputs switching) = 115.5mW + 30.94mW = 146.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.146W * 90.5C/W = 98.2C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
ABLE
6A. T
HERMAL
R
ESISTANCE
JA
FOR
8-
PIN
TSSOP, F
ORCED
C
ONVECTION
JA
by Velocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
153.3C/W
128.5C/W
115.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7C/W
103.3C/W
97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
6B. T
HERMAL
R
ESISTANCE
JA
FOR
8-P
IN
SOIC, F
ORCED
C
ONVECTION
853052AG
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REV. A JULY 1, 2004
10
Integrated
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ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
PRELIMINARY
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
0.935V
(V
CC_MAX
- V
OH_MAX
) = 0.935V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.67V
(V
CC_MAX
- V
OL_MAX
) = 1.67V
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC _MAX
- V
OH_MAX
) =
[(2V - 0.935V)/50
] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.67V)/50
] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
Figure 4. LVPECL Driver Circuit and Termination
VOUT
Q1
VCC - 2V
RL
50
VCC
853052AG
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REV. A JULY 1, 2004
11
Integrated
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Systems, Inc.
ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS853052 is: 110
T
ABLE
7A.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
T
ABLE
7B.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
SOIC
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
153.3C/W
128.5C/W
115.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7C/W
103.3C/W
97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
853052AG
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REV. A JULY 1, 2004
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Integrated
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ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
8 L
EAD
TSSOP
T
ABLE
8A. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-187
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
m
u
m
i
n
i
M
m
u
m
i
x
a
M
N
8
A
-
-
0
1
.
1
1
A
0
5
1
.
0
2
A
9
7
.
0
7
9
.
0
b
2
2
.
0
8
3
.
0
c
8
0
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0
3
2
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0
D
C
I
S
A
B
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3
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S
A
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0
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S
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S
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L
0
4
.
0
0
8
.
0
0
8
a
a
a
-
-
0
1
.
0
T
ABLE
8B. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-012
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2
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3
3
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2
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2
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0
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5
0
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5
2
.
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0
4
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2
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0
8
P
ACKAGE
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UTLINE
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FOR
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EAD
SOIC
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
13
Integrated
Circuit
Systems, Inc.
ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
PRELIMINARY
T
ABLE
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-
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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