Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Clock Input Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- ECL DC Characteristics
- AC Characteristics
- Parameter Measurement Information
- Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Propagation Delay Diagram
- Part-to-Part Skew Diagram
- Output Rise/Fall Time Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Termination for 3.3V LVPECL Outputs
- Termination for 2.5V LVPECL Outputs
- LVPECL Clock Input Interface
- Schematic Example
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculation & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
1
Integrated
Circuit
Systems, Inc.
ICS853058
8:1, D
IFFERENTIAL
-
TO
-
3.3V
OR
2.5V LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS853058 is an 8:1 Differential-to-3.3V or
2.5V LVPECL / ECL Clock Multiplexer which can
operate up to 2.5GHz and is a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The ICS853058 has 8 differ-
ential selectable clock inputs. The PCLK, nPCLK input pairs
can accept LVPECL, LVDS, CML or SSTL levels. The fully dif-
ferential architecture and low propagation delay make it ideal
for use in clock distribution circuits. The select pins have inter-
nal pulldown resistors. The SEL2 pin is the most significant bit
and the binary number applied to the select pins will select the
same numbered data input (i.e., 000 selects PCLK0, nPCLK0).
F
EATURES
High speed 8:1 differential multiplexer
1 differential 3.3V or 2.5V LVPECL output
8 selectable differential PCLK, nPCLK inputs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: 2.5GHz
Translates any single ended input signal to
LVPECL levels with resistor bias on nPCLKx input
Part-to-part skew: TBD
Propagation delay: 620ps (typical)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.465V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.465V to -2.375V
-40C to 85C ambient operating temperature
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
HiPerClockSTM
ICS
ICS853058
24-Lead, 173-MIL TSSOP
4.4mm x 7.8mm x 0.92mm body package
G Package
Top View
PCLK0
nPCLK0
PCLK1
nPCLK1
V
CC
SEL0
SEL1
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
PCLK7
nPCLK7
PLCK6
nPCLK6
V
CC
Q0
nQ0
V
EE
PCLK5
nPCLK5
PCLK4
nPCLK4
PCLK0
nPCLK0
PCLK1
nPCLK1
PCLK2
nPCLK2
PCLK3
nPCLK3
000
011
001
010
SEL1 SEL0
Q0
nQ0
PCLK4
nPCLK4
PCLK5
nPCLK5
PCLK6
nPCLK6
PCLK7
nPCLK7
SEL2
100
111
101
110
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
2
Integrated
Circuit
Systems, Inc.
ICS853058
8:1, D
IFFERENTIAL
-
TO
-
3.3V
OR
2.5V LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
T
ABLE
1. P
IN
D
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853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
3
Integrated
Circuit
Systems, Inc.
ICS853058
8:1, D
IFFERENTIAL
-
TO
-
3.3V
OR
2.5V LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3. C
LOCK
I
NPUT
F
UNCTION
T
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853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
4
Integrated
Circuit
Systems, Inc.
ICS853058
8:1, D
IFFERENTIAL
-
TO
-
3.3V
OR
2.5V LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375
TO
3.465V; V
EE
= 0V
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-
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= 2.375
TO
3.465V; V
EE
= 0V
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3
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C
C
V
=
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2
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2
=
0
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1
A
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o
L
t
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p
n
I
2
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E
S
:
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E
S
V
C
C
V
,
V
5
6
4
.
3
=
N
I
,
V
0
=
V
C
C
V
,
V
5
2
6
.
2
=
N
I
V
0
=
0
5
1
-
A
Supply Voltage, V
CC
4.6V (LVPECL mode, V
EE
= 0)
Negative Supply Voltage, V
EE
-4.6V (ECL mode, V
CC
= 0)
Inputs, V
I
(LVPECL mode)
-0.5V to V
CC
+ 0.5V
Inputs, V
I
(ECL mode)
0.5V to V
EE
- 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Operating Temperature Range, TA -40C to +85C
Storage Temperature, T
STG
-65C to 150C
Package Thermal Impedance,
JA
70C/W (0 mps)
(Junction-to-Ambient)
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
5
Integrated
Circuit
Systems, Inc.
ICS853058
8:1, D
IFFERENTIAL
-
TO
-
3.3V
OR
2.5V LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
T
ABLE
4D. ECL DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3.465V
TO
-2.375V
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ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3.465V
TO
-2.375V
OR
V
CC
= 2.375
TO
3.465V; V
EE
= 0V
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r
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d
n
a
t
S
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3
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T
O
N
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
6
Integrated
Circuit
Systems, Inc.
ICS853058
8:1, D
IFFERENTIAL
-
TO
-
3.3V
OR
2.5V LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
P
ROPAGATION
D
ELAY
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
R
ISE
/F
ALL
T
IME
nQx
Qx
nQy
Qy
PART 1
PART 2
tsk(pp)
V
CMR
Cross Points
V
PP
V
EE
V
CC
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
OD
t
PD
nPCLK0:7
PCLK0:7
nQ0
Q0
SCOPE
Qx
nQx
LVPECL
2V
V
CC
V
EE
nPCLK0:7
PCLK0:7
-1.465V to -0.375V
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
7
Integrated
Circuit
Systems, Inc.
ICS853058
8:1, D
IFFERENTIAL
-
TO
-
3.3V
OR
2.5V LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
A
PPLICATION
I
NFORMATION
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
T
ERMINATION
FOR
3.3V LVPECL O
UTPUTS
VCC
R2
1K
V_REF
C1
0.1u
R1
1K
Single Ended Clock Input
PCLK
nPCLK
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
8
Integrated
Circuit
Systems, Inc.
ICS853058
8:1, D
IFFERENTIAL
-
TO
-
3.3V
OR
2.5V LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very close to
ground level. The R3 in Figure 3B can be eliminated and the
termination is shown in
Figure 3C.
F
IGURE
3C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
F
IGURE
3B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
F
IGURE
3A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
Zo = 50 Ohm
R1
250
+
-
2.5V
2,5V LVPECL
Driv er
R4
62.5
R3
250
Zo = 50 Ohm
2.5V
VCC=2.5V
R1
50
R3
18
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
VCC=2.5V
2.5V
R2
50
2,5V LVPECL
Driv er
VCC=2.5V
R1
50
R2
50
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
+
-
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
9
Integrated
Circuit
Systems, Inc.
ICS853058
8:1, D
IFFERENTIAL
-
TO
-
3.3V
OR
2.5V LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
LVPECL C
LOCK
I
NPUT
I
NTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
SWING
and V
OH
must meet the V
PP
and V
CMR
input requirements.
Figures 4A to 4E show inter-
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
F
IGURE
4A. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
CML D
RIVER
F
IGURE
4B. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
AN
SSTL
IN
D
RIVER
F
IGURE
4C. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
F
IGURE
4D. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVDS D
RIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
F
IGURE
4E. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
3.3V
R5
100 - 200
3.3V
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
PC L K /n PC LK
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
10
Integrated
Circuit
Systems, Inc.
ICS853058
8:1, D
IFFERENTIAL
-
TO
-
3.3V
OR
2.5V LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
S
CHEMATIC
E
XAMPLE
An application schematic example of ICS853058 is shown in
Figure 5. The inputs can accept various types of differential sig-
nals. In this example, the inputs are driven by 3.3V LVPECL
drivers. The ICS853058 output is an LVPECL driver. An example
of LVPECL terminations is shown this schematic. Other termi-
nation approaches are available in the LVPECL Termination
Application Note. It is recommended at least one decoupling ca-
pacitor per power pin. The decoupling capacitor should be low
ESR and located as close as possible to the power pin.
F
IGURE
5. ICS853058 S
CHEMATIC
E
XAMPLE
R3
50
Zo = 50
Zo = 50
RD2
1K
C1
0.1u
To Logic
Input
pins
RD1
Not Install
R8
50
C2
0.1u
Zo = 50
U1
ICS853058
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
24
23
22
21
PCLK0
nPCLK0
PCLK1
nPCLK1
VCC
SEL0
SEL1
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
nPCLK4
PCLK4
nPCLK5
PCLK5
GND
nQ0
Q0
VCC
PCLK7
nPCLK7
PCLK6
nPCLK6
3.3V
Zo = 50
R5
50
RU2
Not Install
R6
50
Zo = 50
Set Logic
Input to
'0'
3.3V
Logic Control Input Examples
R7
50
R1
50
R4
50
LVPECL
R9
50
Set Logic
Input to
'1'
R2
50
Zo = 50
RU1
1K
LVPECL
+
-
LVPECL
To Logic
Input
pins
3.3V
3.3V
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
11
Integrated
Circuit
Systems, Inc.
ICS853058
8:1, D
IFFERENTIAL
-
TO
-
3.3V
OR
2.5V LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853058.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853058 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V 5% =
3.465V
, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
=
3.465V
* 38mA = 131.67mW
Power (outputs)
MAX
= 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 1 * 30.94mW = 30.94mW
Total Power
_MAX
(
3.465V
, with all outputs switching) = 131.67mW + 30.94mW = 162.61mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.163W * 65C/W = 95.6C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
JA
by Velocity (Meters per Second)
T
ABLE
6. T
HERMAL
R
ESISTANCE
JA
FOR
24-P
IN
TSSOP F
ORCED
C
ONVECTION
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
12
Integrated
Circuit
Systems, Inc.
ICS853058
8:1, D
IFFERENTIAL
-
TO
-
3.3V
OR
2.5V LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
0.935V
(V
CCO_MAX
- V
OH_MAX
) = 0.935V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.67V
(V
CCO_MAX
- V
OL_MAX
) = 1.67V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.935V)/50
] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.67V)/50
] * 1.67V = 11.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
F
IGURE
6. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
VCCO - 2V
Q1
VOUT
RL
50
VCCO
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
13
Integrated
Circuit
Systems, Inc.
ICS853058
8:1, D
IFFERENTIAL
-
TO
-
3.3V
OR
2.5V LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS853058 is: 326
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
14
Integrated
Circuit
Systems, Inc.
ICS853058
8:1, D
IFFERENTIAL
-
TO
-
3.3V
OR
2.5V LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-153
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
24 L
EAD
TSSOP
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
m
u
m
i
n
i
M
m
u
m
i
x
a
M
N
4
2
A
-
-
0
2
.
1
1
A
5
0
.
0
5
1
.
0
2
A
0
8
.
0
5
0
.
1
b
9
1
.
0
0
3
.
0
c
9
0
.
0
0
2
.
0
D
0
7
.
7
0
9
.
7
E
C
I
S
A
B
0
4
.
6
1
E
0
3
.
4
0
5
.
4
e
C
I
S
A
B
5
6
.
0
L
5
4
.
0
5
7
.
0
0
8
a
a
a
-
-
0
1
.
0
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
15
Integrated
Circuit
Systems, Inc.
ICS853058
8:1, D
IFFERENTIAL
-
TO
-
3.3V
OR
2.5V LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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