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853210AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 12, 2003
1
Integrated
Circuit
Systems, Inc.
ICS853210
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS853210 is a low skew, high perfor-
mance dual 1 - t o - 5 Differential-to-2.5V/3.3V
LVPECL/ECL Fanout Buffer and a member of
the HiPerClockSTM family of High Performance
Clock Solutions from ICS. The ICS853210
is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and par t-to-par t skew
characteristics make the ICS853210 ideal for those clock
distribution applications demanding well defined perfor-
mance and repeatability.
F
EATURES
2 differential 2.5V/3.3V LVPECL / ECL bank outputs
2 differential clock input pairs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: >3GHz
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLKx input
Output skew: 13ps (typical)
Part-to-part skew: 85ps (typical)
Propagation delay: 485ps (typical)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -2.375V to -3.8V
-40C to 85C ambient operating temperature
Pin compatible with MC100EP210 and MC100LVEP210
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
HiPerClockSTM
ICS
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
PCLKA
nPCLKA
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
PCLKB
nPCLKB
ICS853210
24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
QA3
nQA3
QA4
nQA4
QB0
nQB0
QB1
nQB1
V
CCO
QB2
nQB2
QB3
nQB3
QB4
nQB4
V
CCO
V
CCO
nQA2
QA2
nQA1
QA1
nQA0
QA0
V
CCO
V
CC
nc
PCLKA
nPCLKA
VBB
PCLKB
nPCLK
B
V
EE
V
BB
853210AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 12, 2003
2
Integrated
Circuit
Systems, Inc.
ICS853210
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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853210AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 12, 2003
3
Integrated
Circuit
Systems, Inc.
ICS853210
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V; V
EE
= 0V
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4B. LVPECL DC C
HARACTERISTICS
,
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CC
= 3.3V; V
EE
= 0V
A
BSOLUTE
M
AXIMUM
R
ATINGS
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Supply Voltage, V
CC
4.6V (LVPECL mode, V
EE
= 0)
Negative Supply Voltage, V
EE
-4.6V (ECL mode, V
CC
= 0)
Inputs, V
I
(LVPECL mode)
-0.5V to V
CC
+ 0.5V
Inputs, V
I
(ECL mode)
0.5V to V
EE
- 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
V
BB
Sink/Source, I
BB
0.5mA
Operating Temperature Range, TA -40C to +85C
Storage Temperature, T
STG
-65C to 150C
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
(Junction-to-Ambient)
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+
853210AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 12, 2003
4
Integrated
Circuit
Systems, Inc.
ICS853210
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
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T
ABLE
4C. LVPECL DC C
HARACTERISTICS
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V
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= 2.5V; V
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+
853210AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 12, 2003
5
Integrated
Circuit
Systems, Inc.
ICS853210
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -2.375
TO
-3.8V
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CC
= 2.375
TO
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N
853210AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 12, 2003
6
Integrated
Circuit
Systems, Inc.
ICS853210
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ROPAGATION
D
ELAY
V
CMR
Cross Points
V
PP
V
EE
nPCLKA,
nPCLKB
V
CC
PCLKA,
PCLKB
SCOPE
Qx
nQx
LVPECL
2V
-0.375V to -1.8V
tsk(pp)
t
sk(o)
nQx
Qx
nQy
Qy
PART 1
PART 2
nQx
Qx
nQy
Qy
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
tp
LH
tp
HL
nPCLKA,
nPCLKB
QA0:QA4,
QB0:QB4,
nQA0:nQA4,
nQB0:nQB4,
PCLKA,
PCLKB
V
CC
,
V
CCO
V
EE
853210AY
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REV. A NOVEMBER 12, 2003
7
Integrated
Circuit
Systems, Inc.
ICS853210
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
Figure 1A shows an example of the differential input that can
be wired to accept single ended levels. The reference voltage
level V
BB
generated from the device is connected to the
A
PPLICATION
I
NFORMATION
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
LVPECL L
EVELS
F
IGURE
1A. S
INGLE
E
NDED
LVPECL S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
negative input. The C1 capacitor should be located as close
as possible to the input pin.
VCC(or VDD)
CLK_IN
PCLK
nPCLK
VBB
Figure 1B shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
1B. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R2
1K
V_REF
C1
0.1u
R1
1K
Single Ended Clock Input
PCLK
nPCLK
853210AY
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REV. A NOVEMBER 12, 2003
8
Integrated
Circuit
Systems, Inc.
ICS853210
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
3.3V LVPECL O
UTPUTS
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
853210AY
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REV. A NOVEMBER 12, 2003
9
Integrated
Circuit
Systems, Inc.
ICS853210
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very close to
ground level. The R3 in
Figure 3B can be eliminated and the
termination is shown in
Figure 3C.
F
IGURE
3C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driv er
F
IGURE
3B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driv er
Zo = 50 Ohm
+
-
2.5V
F
IGURE
3A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driv er
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
853210AY
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REV. A NOVEMBER 12, 2003
10
Integrated
Circuit
Systems, Inc.
ICS853210
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
LVPECL C
LOCK
I
NPUT
I
NTERFACE
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other
differential signals. Both V
SWING
and V
OH
must meet the V
PP
and V
CMR
input requirements.
Figures 4A to 4E show inter-
face examples for the HiPerClockS PCLKx/nPCLKx input
driven by the most common driver types. The input interfaces
suggested here are examples only. If the driver is from an-
other vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm
the driver termination requirements.
F
IGURE
4A. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
CML D
RIVER
F
IGURE
4B. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
AN
SSTL D
RIVER
F
IGURE
4C. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
F
IGURE
4D. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
3.3V LVDS D
RIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
F
IGURE
4E. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
3.3V
R5
100 - 200
3.3V
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
PC L K /n PC LK
853210AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 12, 2003
11
Integrated
Circuit
Systems, Inc.
ICS853210
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853210.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853210 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.8V * 80mA = 304mW
Power (outputs)
MAX
= 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW
Total Power
_MAX
(3.8V, with all outputs switching) = 304mW + 309.4mW = 613.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.613W * 42.1C/W = 110.8C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
ABLE
6. T
HERMAL
R
ESISTANCE


JA
FOR
32-
PIN
LQFP, F
ORCED
C
ONVECTION
853210AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 12, 2003
12
Integrated
Circuit
Systems, Inc.
ICS853210
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
0.935V
(V
CC_MAX
- V
OH_MAX
) = 0.935V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.67V
(V
CCO_MAX
- V
OL_MAX
) = 1.67V
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO _MAX
- V
OH_MAX
) =
[(2V - 0.935V)/50
] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.67V)/50
] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
Figure 5. LVPECL Driver Circuit and Termination
VCCO - 2V
Q1
VOUT
RL
50
VCCO
853210AY
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REV. A NOVEMBER 12, 2003
13
Integrated
Circuit
Systems, Inc.
ICS853210
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS853210 is:
437
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
853210AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 12, 2003
14
Integrated
Circuit
Systems, Inc.
ICS853210
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EAD
LQFP
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
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B
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U
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A
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2
3
A
-
-
-
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0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
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853210AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 12, 2003
15
Integrated
Circuit
Systems, Inc.
ICS853210
L
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S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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