Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Clock Input Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- Differential DC Characteristics
- LVPECL DC Characteristics
- AC Characteristics
- Additive Phase Jitter
- Parameter Measurement Information
- Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Part-to-Part Skew Diagram
- Output Skew Diagram
- Output Rise/Fall Time Diagram
- Propagation Delay Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Termination for 3.3V LVPECL Outputs
- Termination for 2.5V LVPECL Outputs
- Differential Clock Input Interface
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
85310AYI-21
www.icst.com/products/hiperclocks.html
REV. D JUNE 30, 2005
1
Integrated
Circuit
Systems, Inc.
ICS85310I-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS85310I-21 is a low skew, high perfor-
mance dual 1 - t o - 5 Differential-to-2.5V/3.3V
ECL/LVPECL Fanout Buffer and a member of
the HiPerClockSTM
family of High Performance
Clock Solutions from ICS. The CLKx, nCLKx
pairs can accept most standard differential input levels.
The ICS85310I-21 is characterized to operate from either a
2.5V or a 3.3V power supply. Guaranteed output and part-
to-part skew characteristics make the ICS85310I-21 ideal
for those clock distribution applications demanding well
defined performance and repeatability.
F
EATURES
2 differential 2.5V/3.3V LVPECL / ECL bank outputs
2 differential clock input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 700MHz
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nCLKx input
Output skew: 25ps (typical)
Part-to-part skew: 270ps (typical)
Propagation delay: 1.7ns (typical)
Additive phase jitter, RMS: <0.13ps (typical)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.8V to -2.375V
-40C to 85C ambient operating temperature
Lead-Free package fully RoHS complaint
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
HiPerClockSTM
ICS
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
QA3
nQA3
QA4
nQA4
QB0
nQB0
QB1
nQB1
V
CC
nc
CLKA
nCLKA
nc
CLKB
nCLKB
V
EE
V
CCO
QB2
nQB2
QB3
nQB3
QB4
nQB4
V
CCO
V
CCO
nQA2
QA2
nQA1
QA1
nQA0
QA0
V
CCO
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS85310I-21
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
CLKA
nCLKA
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
CLKB
nCLKB
85310AYI-21
www.icst.com/products/hiperclocks.html
REV. D JUNE 30, 2005
2
Integrated
Circuit
Systems, Inc.
ICS85310I-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
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85310AYI-21
www.icst.com/products/hiperclocks.html
REV. D JUNE 30, 2005
3
Integrated
Circuit
Systems, Inc.
ICS85310I-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
T
ABLE
4A. P
OWER
S
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HARACTERISTICS
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CC
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CCO
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ABLE
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4C. LVPECL DC C
HARACTERISTICS
,
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CC
= V
CCO
= 2.375V
TO
3.8V, T
A
= -40C
TO
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N
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o
t
O
C
C
.
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2
-
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Negative Supply Voltage, V
EE
-4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Operating Temperature Range, TA -40C to +85C
Storage Temperature, T
STG
-65C to 150C
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
(Junction-to-Ambient)
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
85310AYI-21
www.icst.com/products/hiperclocks.html
REV. D JUNE 30, 2005
4
Integrated
Circuit
Systems, Inc.
ICS85310I-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCO
= 2.375V
TO
3.8V, T
A
= -40C
TO
85C
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85310AYI-21
www.icst.com/products/hiperclocks.html
REV. D JUNE 30, 2005
5
Integrated
Circuit
Systems, Inc.
ICS85310I-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
A
DDITIVE
P
HASE
J
ITTER
Additive Phase Jitter, RMS
@ 155.52MHz = <0.13ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dB
c
/
H
Z
85310AYI-21
www.icst.com/products/hiperclocks.html
REV. D JUNE 30, 2005
6
Integrated
Circuit
Systems, Inc.
ICS85310I-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ROPAGATION
D
ELAY
V
CMR
Cross Points
V
PP
V
EE
nCLKA, nCLKB
V
CC
CLKA, CLKB
SCOPE
Qx
nQx
LVPECL
2V
-0.375V to -1.8V
tsk(pp)
tsk(o)
nQx
Qx
nQy
Qy
PART 1
PART 2
nQx
Qx
nQy
Qy
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
t
PD
nCLKA,
nCLKB
QAx,
QBx
nQAx,
nQBx
CLKA,
CLKB
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
QA0:QA4,
QB0:QB4
nQA0:nQA4,
nQB0:nQB4
V
EE
V
CC
,
V
CCO
85310AYI-21
www.icst.com/products/hiperclocks.html
REV. D JUNE 30, 2005
7
Integrated
Circuit
Systems, Inc.
ICS85310I-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
3.3V LVPECL O
UTPUTS
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLKx
nCLKx
VCC
85310AYI-21
www.icst.com/products/hiperclocks.html
REV. D JUNE 30, 2005
8
Integrated
Circuit
Systems, Inc.
ICS85310I-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
T
ERMINATION
FOR
2.5V LVPECL O
UTPUTS
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very close to
ground level. The R3 in Figure 3B can be eliminated and the
termination is shown in
Figure 3C.
F
IGURE
3C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driv er
F
IGURE
3B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driv er
Zo = 50 Ohm
+
-
2.5V
F
IGURE
3A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driv er
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
85310AYI-21
www.icst.com/products/hiperclocks.html
REV. D JUNE 30, 2005
9
Integrated
Circuit
Systems, Inc.
ICS85310I-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
F
IGURE
4C. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
4B. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
4D. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 4A to 4E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
4A. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 4A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
F
IGURE
4E. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
85310AYI-21
www.icst.com/products/hiperclocks.html
REV. D JUNE 30, 2005
10
Integrated
Circuit
Systems, Inc.
ICS85310I-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85310I-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85310I-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.8V * 120mA = 456mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 30.2mW = 302mW
Total Power
_MAX
(3.8V, with all outputs switching) = 4564mW + 302mW = 758mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used
. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.758W * 42.1C/W = 117C. This is below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
ABLE
6. T
HERMAL
R
ESISTANCE
JA
FOR
32-
PIN
LQFP, F
ORCED
C
ONVECTION
85310AYI-21
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REV. D JUNE 30, 2005
11
Integrated
Circuit
Systems, Inc.
ICS85310I-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
1.0V
(V
CCO_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO _MAX
- V
OH_MAX
) =
[(2V - 1V)/50
] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
Figure 5. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
85310AYI-21
www.icst.com/products/hiperclocks.html
REV. D JUNE 30, 2005
12
Integrated
Circuit
Systems, Inc.
ICS85310I-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS85310I-21 is: 1216
Pin compatible with MC100LVEP210
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85310AYI-21
www.icst.com/products/hiperclocks.html
REV. D JUNE 30, 2005
13
Integrated
Circuit
Systems, Inc.
ICS85310I-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EAD
LQFP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
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85310AYI-21
www.icst.com/products/hiperclocks.html
REV. D JUNE 30, 2005
14
Integrated
Circuit
Systems, Inc.
ICS85310I-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
85310AYI-21
www.icst.com/products/hiperclocks.html
REV. D JUNE 30, 2005
15
Integrated
Circuit
Systems, Inc.
ICS85310I-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
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