Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- LVPECL Power Supply DC Characteristics
- LVPECL DC Characteristics
- ECL Power Supply DC Characteristics
- ECL DC Characteristics
- AC Characteristics
- Additive Phase Jitter
- Parameter Measurement Information
- Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Output Skew Diagram
- Part-to-Part Skew Diagram
- Propagation Delay Diagram
- Output Rise/Fall Time Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Termination for LVPECL Outputs
- PCLK/nPCLK Clock Input Interface
- HiPerClockS PCLK/nPCLK Input Driven by a CML Driver Diagram
- HiPerClockS PCLK/nPCLK Input Driven by an SSTL Driver Diagram
- HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver Diagram
- HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVDS Driver Diagram
- HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver w/AC Couple Diagram
- Schematic Example
- Power Considerations
- Power Dissipation
- Junciton Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
853111AV-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
1
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS853111-01 is a low skew, high perfor-
mance 1-to-9 Differential-to-3.3V LVPECL/ECL
Fa n o u t B u f f e r a n d a m e m b e r o f t h e
HiPerClock S TM
family of High Perfor mance
Clock Solutions from ICS. The PCLK, nPCLK
pair can accept LVPECL, CML and SSTL differential input
levels. The ICS853111-01 is characterized to operate from
a 3.3V power supply. Guaranteed output and par t-to-par t
skew characteristics make the ICS853111-01 ideal for
those clock distribution applications demanding well
defined performance and repeatability.
F
EATURES
9 differential 3.3V LVPECL / ECL outputs
1 differential LVPECL input pair
PLCK, nPLCK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: >2GHz (typical)
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
Additive phase jitter, RMS: 0.03ps (typical)
Output skew: 35ps (maximum)
Part-to-part skew: 300ps (maximum)
Propagation delay: 675ps (maximum)
LVPECL mode operating voltage supply range:
V
CC
= 3V to 3.8V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3V to -3.8V
-40C to 85C ambient operating temperature
Lead-Free package RoHS compliant
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
HiPerClockSTM
ICS
28-Lead PLCC
11.6mm x 11.4mm x 4.1mm package body
V Package
Top View
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
PCLK
nPCLK
ICS853111-01
5 6 7 8 9 10 11
26
27
28
1
2
3
4
18
17
16
15
14
13
12
V
EE
nc
PCLK
V
CC
nPCLK
V
BB
nc
nQ8
Q8
nQ7
V
CCO
Q7
nQ6
Q6
nQ2
Q2
nQ1
V
CCO
Q1
nQ0
Q0
Q3
nQ3
Q4
V
CCO
nQ4
Q5
nQ5
V
BB
25 24 23 22 21 20 19
853111AV-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
2
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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853111AV-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
3
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
T
ABLE
3A. LVPECL P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3V
TO
3.8V; V
EE
= 0V
Table 3B. LVPECL DC Characteristics,
V
CC
= 3.3V; V
EE
= 0V
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A
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A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V (LVPECL mode, V
EE
= 0)
Negative Supply Voltage, V
EE
-4.6V (LVECL mode, V
CC
= 0)
Inputs, V
I
(LVPECL mode)
-0.5V to V
CC
+ 0.5 V
Inputs, V
I
(LVECL mode)
0.5V to V
EE
- 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
V
BB
Sink/Source, I
BB
0.5mA
Operating Temperature Range, TA -40C to +85C
Storage Temperature, T
STG
-65C to 150C
Package Thermal Impedance,
JA
37.8C/W (0 lfpm)
(Junction-to-Ambient)
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
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.
V
3
.
0
+
853111AV-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
4
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
Table 3D. ECL DC Characteristics,
V
CC
= 0V; V
EE
= -3V to -3.8V
T
ABLE
4. AC C
HARACTERISTICS
,
V
CC
= 3V
TO
3.8V; V
EE
= 0V
OR
V
CC
= 0V; V
EE
= -3V
TO
-3.8V
T
ABLE
3C. ECL P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3V
TO
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.
V
3
.
0
+
853111AV-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
5
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
A
DDITIVE
P
HASE
J
ITTER
Input/Output Additive
Phase Jitter
at 155.52MHz
= 0.03ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dBc/H
Z
853111AV-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
6
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
S
KEW
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.3V
P
ART
-
TO
-P
ART
S
KEW
tsk(o)
Qy
Qx
V
CMR
Cross Points
V
PP
V
EE
PCLK
nPCLK
V
CC
nQy
nQx
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
t
PD
PCLK
nPCLK
P
ROPAGATION
D
ELAY
nQx
Qx
nQy
Qy
PART 1
PART 2
tsk(pp)
O
UTPUT
R
ISE
/F
ALL
T
IME
nQ0:nQ8
Q0:Q8
V
EE
V
CC
853111AV-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
7
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
A
PPLICATION
I
NFORMATION
Figure 1 shows an example of the differential input that can
be wired to accept single ended levels. The reference voltage
level V
BB
generated from the device is connected to the
F
IGURE
1. S
INGLE
E
NDED
LVPECL S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
negative input. The C1 capacitor should be located as close
as possible to the input pin.
PCLK
nPCLK
VBB
C1
0.1u
CLK_IN
VCC
853111AV-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
8
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
LVPECL C
LOCK
I
NPUT
I
NTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
SWING
and V
OH
must meet the V
PP
and V
CMR
input requirements.
Figures 3A to 3F show interface
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver ter-
mination requirements.
F
IGURE
3A.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
AN
O
PEN
C
OLLECTOR
CML D
RIVER
F
IGURE
3B. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
B
UILT
-I
N
P
ULLUP
CML D
RIVER
F
IGURE
3C. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
F
IGURE
3F.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVDS D
RIVER
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
F
IGURE
3E.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
AN
SSTL D
RIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
F
IGURE
3D. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
3.3V
3.3V
CML Built-In Pullup
R1
100
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
Zo = 50 Ohm
Zo = 50 Ohm
R2
50
Zo = 50 Ohm
C1
R1
50
C2
PC L K /n PC LK
R5
100 - 200
Zo = 50 Ohm
R6
100 - 200
PCLK
nPCLK
VBB
3.3V LVPECL
3.3V
3.3V
LVDS
3.3V
Zo = 50 Ohm
3.3V
PCLK
nPCLK
VBB
R2
1K
C2
R1
1K
R5
100
C1
PC L K /n PC L K
Zo = 50 Ohm
853111AV-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
9
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
S
CHEMATIC
E
XAMPLE
This application note provides general design guide using
ICS853111-01 LVPECL buffer.
Figure 4 shows a schematic
F
IGURE
4. E
XAMPLE
ICS853111-01 LVPECL C
LOCK
O
UTPUT
B
UFFER
S
CHEMATIC
example of the ICS853111-01 LVPECL clock buffer. In this
example, the input is driven by an LVPECL driver.
C4
0.1uF
C6 (Option)
0.1u
Zo = 50
R7
50
Zo = 50
R2
50
VCC
R1
50
VCC
VCC=3.3V
C7 (Option)
0.1u
R3
50
(U1-16)
U1
ICS853111
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
VCC
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VEE
VC
C
O
nQ
9
Q9
nQ
8
Q8
nQ
7
Q7
VC
C
O
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
VC
C
O
Q0
nQ
0
Q1
nQ
1
Q2
nQ
2
VC
C
O
R4
1K
Zo = 50
C2
0.1uF
(U1-9)
R8
50
Zo = 50 Ohm
C8 (Option)
0.1u
+
-
C5
0.1uF
R10
50
R11
50
3.3V LVPECL
+
-
VCC
(U1-32)
R13
50
C1
0.1uF
Zo = 50 Ohm
R9
50
C3
0.1uF
(U1-25)
VCC
Zo = 50
(U1-1)
853111AV-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
10
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8C/W
31.1C/W
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853111-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853111-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.8V * 75mA = 285mW
Power (outputs)
MAX
= 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 9 * 30.94mW = 278.5mW
Total Power
_MAX
(3.8V, with all outputs switching) = 285mW + 278.5mW = 563.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.564W * 31.1C/W = 102C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
ABLE
5. T
HERMAL
R
ESISTANCE
JA
FOR
28-
PIN
PLCC, F
ORCED
C
ONVECTION
853111AV-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
11
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
0.935V
(V
CCO_MAX
- V
OH_MAX
) = 0.935V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.67V
(V
CCO_MAX
- V
OL_MAX
) = 1.67V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.935V)/50
] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.67V)/50
] * 1.67V = 11.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
Figure 5. LVPECL Driver Circuit and Termination
VCCO - 2V
Q1
VOUT
RL
50
VCCO
853111AV-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
12
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS853111-01 is: 265
Pin compatible with MC100LVE111
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
28 L
EAD
PLCC
JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8C/W
31.1C/W
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
853111AV-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
13
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- V S
UFFIX
FOR
28 L
EAD
PLCC
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
M
U
M
I
N
I
M
M
U
M
I
X
A
M
N
8
2
A
9
1
.
4
7
5
.
4
1
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9
2
.
2
5
0
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2
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7
5
.
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2
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3
4
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1
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5
8
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5
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E
2
3
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1
7
5
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T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-018
853111AV-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
14
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademark. HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
853111AV-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
15
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
T
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