Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Clock Input Function Table
- Control Input Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVPECL 3.3V DC Characteristics
- LVPECL 2.5V DC Characteristics
- ECL DC Characteristics
- AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Part-to-Part Skew Diagram
- Output Skew Diagram
- Output Rise/Fall Time Diagram
- Propagation Delay Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended LVCMOS Levels
- Wiring the Differential Input to Accept Single Ended LVPECL Levels
- Termination for 3.3V LVPECL Outputs
- Termination for 2.5V LVPECL Outputs
- LVPECL Clock Input Interface
- HiPerClockS PCLK/nPCLK Input Driven by a CML Driver Diagram
- HiPerClockS PCLK/nPCLK Input Driven by an SSTL Driver Diagram
- HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver Diagram
- HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVDS Driver Diagram
- HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver w/AC Couple Diagram
- Schematic Example
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
1
Integrated
Circuit
Systems, Inc.
ICS853111
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
G
ENERAL
D
ESCRIPTION
The ICS853111 is a low skew, high perfor-
mance 1-to-10 Differential-to-2.5V/3.3V LVPECL/
ECL Fanout Buffer and a member of the
HiPerClockSTM family of High Performance
Clock Solutions from ICS. The ICS853111
is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853111 ideal for those clock
distribution applications demanding well defined perfor-
mance and repeatability.
F
EATURES
10 differential 2.5V/3.3V LVPECL / ECL outputs
2 selectable differential input pairs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: >3GHz
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
Output skew: TBD
Part-to-part skew: TBD
Propagation delay: TBD
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.8V to -2.375V
-40C to 85C ambient operating temperature
Pin compatible with MC100EP111 and MC100LVEP111
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
HiPerClockSTM
,&6
24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
V
CCO
Q7
nQ7
Q8
nQ8
Q9
nQ9
V
CCO
V
CCO
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
CCO
ICS853111
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
PCLK0
nPCLK0
0
1
PCLK1
nPCLK1
CLK_SEL
V
BB
V
CC
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK
1
V
EE
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
2
Integrated
Circuit
Systems, Inc.
ICS853111
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
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853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
3
Integrated
Circuit
Systems, Inc.
ICS853111
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375
TO
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+
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V (LVPECL mode, V
EE
= 0)
Negative Supply Voltage, V
EE
-4.6V (ECL mode, V
CC
= 0)
Inputs, V
I
(LVPECL mode)
-0.5V to V
CC
+ 0.5 V
Inputs, V
I
(ECL mode)
0.5V to V
EE
- 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
V
BB
Sink/Source, I
BB
0.5mA
Operating Temperature Range, TA -40C to +85C
Storage Temperature, T
STG
-65C to 150C
Package Thermal Impedance,
JA
37.8C/W (0 lfpm)
(Junction-to-Ambient)
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
4
Integrated
Circuit
Systems, Inc.
ICS853111
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
4C. ECL DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3.8V
TO
-2.375V
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.5V; V
EE
= 0V
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s
r
o
F
:
4
E
T
O
N
V
s
i
C
C
.
V
3
.
0
+
853111AY
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REV. D JULY 22, 2003
5
Integrated
Circuit
Systems, Inc.
ICS853111
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3.8V
TO
-2.375V
OR
V
CC
= 2.375
TO
3.8V; V
EE
= 0V
l
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b
m
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T
O
N
853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
6
Integrated
Circuit
Systems, Inc.
ICS853111
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ROPAGATION
D
ELAY
V
CMR
Cross Points
V
PP
V
EE
nCLK0, nCLK1
V
CC
CLK0, CLK1
SCOPE
Qx
nQx
LVPECL
V
CC
, V
CCO
= 2V
V
EE
= -0.375V to -1.8V
tsk(pp)
tsk(o)
nQx
Qx
nQy
Qy
PART 1
PART 2
nQx
Qx
nQy
Qy
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
t
PD
nCLK0,
nCLK1
Q0:Q9
nQ0:nQ9
CLK0,
CLK1
853111AY
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REV. D JULY 22, 2003
7
Integrated
Circuit
Systems, Inc.
ICS853111
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
F
IGURE
2A. S
INGLE
E
NDED
LVCMOS S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
Figure 2A shows an example of the differential input that can
be wired to accept single ended LVCMOS levels. The reference
voltage level V
BB
generated from the device is connected to
A
PPLICATION
I
NFORMATION
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
LVCMOS L
EVELS
the negative input. The C1 capacitor should be located as close
as possible to the input pin.
F
IGURE
2B. S
INGLE
E
NDED
LVPECL S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
Figure 2B shows an example of the differential input that can
be wired to accept single ended LVPECL levels. The reference
voltage level V
BB
generated from the device is connected to
the negative input. The C1 capacitor should be located as close
as possible to the input pin.
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
LVPECL L
EVELS
CLK_IN
C1
0.1uF
VDD(or VCC)
+
-
VBB
VCC
R2
1K
V_REF
C1
0.1u
R1
1K
Single Ended Clock Input
PCLK
nPCLK
853111AY
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REV. D JULY 22, 2003
8
Integrated
Circuit
Systems, Inc.
ICS853111
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
F
OUT
F
IN
5
2 Z
o
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o
= 50
Z
o
= 50
RTT =
1
(V
OH
+ V
OL
/ V
CC
2) 2
Z
o
Z
o
= 50
Z
o
= 50
50
50
RTT
V
CC
- 2V
F
IN
F
OUT
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
T
ERMINATION
FOR
3.3V LVPECL O
UTPUTS
853111AY
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REV. D JULY 22, 2003
9
Integrated
Circuit
Systems, Inc.
ICS853111
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 3A and Figure 4B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very close to
ground level. The R3 in
Figure 4B can be eliminated and the
termination is shown in
Figure 4C.
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driv er
F
IGURE
4B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driv er
Zo = 50 Ohm
+
-
2.5V
F
IGURE
4A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driv er
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
F
IGURE
4C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
853111AY
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REV. D JULY 22, 2003
10
Integrated
Circuit
Systems, Inc.
ICS853111
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
LVPECL C
LOCK
I
NPUT
I
NTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
SWING
and V
OH
must meet the V
PP
and V
CMR
input requirements.
Figures 5A to 5E show inter-
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
F
IGURE
5A. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
CML D
RIVER
F
IGURE
5B. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
AN
SSTL D
RIVER
F
IGURE
5C. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
F
IGURE
5D. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
3.3V LVDS D
RIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
F
IGURE
5E. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
3.3V
R5
100 - 200
3.3V
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
853111AY
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REV. D JULY 22, 2003
11
Integrated
Circuit
Systems, Inc.
ICS853111
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS853111 is: 1340
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
S
CHEMATIC
E
XAMPLE
This application note provides general design guide using
ICS853111 LVPECL buffer.
Figure 6 shows a schematic ex-
ample of the ICS853111 LVPECL clock buffer. In this example,
F
IGURE
6. E
XAMPLE
ICS853111 LVPECL C
LOCK
O
UTPUT
B
UFFER
S
CHEMATIC
the input is driven by an LVPECL driver. CLK_SEL is set at logic
high to select PCLK0/nPCLK0 input.
C4
0.1uF
C6 (Option)
0.1u
Zo = 50
R7
50
Zo = 50
R2
50
VCC
R1
50
VCC
VCC=3.3V
C7 (Option)
0.1u
R3
50
(U1-16)
U1
ICS853111
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
VCC
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VEE
V
CCO
nQ
9
Q9
nQ
8
Q8
nQ
7
Q7
V
CCO
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
V
CCO
Q0
nQ
0
Q1
nQ
1
Q2
nQ
2
V
CCO
R4
1K
Zo = 50
C2
0.1uF
(U1-9)
R8
50
Zo = 50 Ohm
C8 (Option)
0.1u
+
-
C5
0.1uF
R10
50
R11
50
3.3V LVPECL
+
-
VCC
(U1-32)
R13
50
C1
0.1uF
Zo = 50 Ohm
R9
50
C3
0.1uF
(U1-25)
VCC
Zo = 50
(U1-1)
853111AY
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REV. D JULY 22, 2003
12
Integrated
Circuit
Systems, Inc.
ICS853111
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
P
ACKAGE
O
UTLINE
- Y S
UFFIX
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
3
A
-
-
-
-
0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
9
0
.
0
-
-
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
.
f
e
R
0
6
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
.
f
e
R
0
6
.
5
e
C
I
S
A
B
0
8
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
q
0
-
-
7
c
c
c
-
-
-
-
0
1
.
0
853111AY
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REV. D JULY 22, 2003
13
Integrated
Circuit
Systems, Inc.
ICS853111
L
OW
S
KEW
, 1-
TO
-10
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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