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Электронный компонент: ICS85314AGI-11LF

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85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
1
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS85314I-11 is a low skew, high perfor-
mance 1-to-5 Differential-to-2.5V/3.3V LVPECL
fanout buffer and a member of the HiPerClockSTM
family of High Performance Clock Solutions from
ICS. The ICS85314I-11 has two selectable dif-
ferential clock inputs. The CLK0, nCLK0 and CLK1, nCLK1
pairs can accept most standard differential input levels. The
clock enable is internally synchronized to eliminate runt clock
pulses on the outputs during asynchronous asser tion/
deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make
the ICS85314I-11 ideal for those applications demanding well
defined performance and repeatability.
F
EATURES
5 differential 2.5V/3.3V LVPECL outputs
Selectable differential CLKx, nCLKx inputs
CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the
following differential input levels: LVPECL, LVDS, LVHSTL,
HCSL, SSTL
Maximum output frequency: 700MHz
Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
Output skew: 30ps (maximum)
Part-to-part skew: 350ps (maximum)
Propagation delay: 1.8ns (maximum)
RMS phase jitter @ 155.52MHz (12kHz - 20MHz):
0.05ps (typical)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
-40C to 85C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
nCLK_EN
V
CC
nCLK1
CLK1
RESERVED
nCLK0
CLK0
CLK_SEL
V
EE
HiPerClockSTM
ICS
ICS85314I-11
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
ICS85314I-11
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm Package Body
M Package
Top View
CLK0
nCLK0
CLK1
nCLK1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
0
1
nCLK_EN
CLK_SEL
D
Q
CK
0
1
85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
2
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
3
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
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F
IGURE
1. nCLK_EN T
IMING
D
IAGRAM
Enabled
Disabled
nCLK0, nCLK1
CLK0, CLK1
nCLK_EN
nQ0:nQ4
Q0:Q4
85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
4
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40C
TO
85C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40C
TO
85C
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4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
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EE
= 0V, T
A
= -40C
TO
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T
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N
C
C
.
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3
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0
+
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s
a
d
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n
i
f
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d
s
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e
g
a
t
l
o
v
e
d
o
m
n
o
m
m
o
C
:
2
E
T
O
N
H
I
.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
5
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40C
TO
85C
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40C
TO
85C
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-
85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
6
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
T
YPICAL
P
HASE
N
OISE
AT
155.52MH
Z
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
155.52MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.05ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Raw Phase Noise Data
85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
7
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
S
KEW
D
IFFERENTIAL
I
NPUT
L
EVEL
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
t
PD
P
ROPAGATION
D
ELAY
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
-1.8V -0.375V
t
sk(o)
nQx
Qx
nQy
Qy
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q0:Q4
nQ0:nQ4
V
CMR
Cross Points
V
PP
V
CC
V
EE
CLK0,
CLK1
nCLK0,
nCLK1
CLK0,
CLK1
nCLK0,
nCLK1
Q0:Q4
nQ0:nQ4
V
CC
V
EE
85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
8
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
F
IGURE
2. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
Figure 2
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
ratio of R1 and R2 might need to be adjusted to position the
V_REF in the center of the input voltage swing. For example, if
the input clock swing is only 2.5V and V
CC
= 3.3V, V_REF should
be 1.25V and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VCC
I
NPUTS
:
CLK I
NPUT
:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the CLK input to
ground.
CLK/nCLK I
NPUT
:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
resistor can be tied from
CLK to ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
9
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
F
IGURE
3C. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3B. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3D. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL,
HCSL and other differential signals. Both V
SWING
and V
OH
must
meet the V
PP
and V
CMR
input requirements. Figures 3A to 3E
show interface examples for the HiPerClockS CLK/nCLK in-
put driven by the most common driver types. The input inter-
F
IGURE
3A. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
faces suggested here are examples only. Please consult with
the vendor of the driver component to confirm the driver termi-
nation requirements. For example in
Figure 3A,
the input ter-
mination applies for ICS HiPerClockS LVHSTL drivers. If you
are using an LVHSTL driver from another vendor, use their
termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
F
IGURE
3E. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
10
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
F
IGURE
4B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
4A. LVPECL O
UTPUT
T
ERMINATION
T
ERMINATION
FOR
3.3V LVPECL O
UTPUTS
designed to drive 50
transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion.
Figures 4A and
4B
show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
11
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 5A
and
Figure 5B
show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to ter-
minating 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very
close to ground level. The R3 in Figure 5B can be eliminated
and the termination is shown in
Figure 5C.
F
IGURE
5C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
F
IGURE
5B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
F
IGURE
5A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
Zo = 50 Ohm
R1
250
+
-
2.5V
2,5V LVPECL
Driv er
R4
62.5
R3
250
Zo = 50 Ohm
2.5V
VCC=2.5V
R1
50
R3
18
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
VCC=2.5V
2.5V
R2
50
2,5V LVPECL
Driv er
VCC=2.5V
R1
50
R2
50
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
+
-
85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
12
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85314I-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85314I-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.8V * 80mA = 304mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power
_MAX
(3.465V, with all outputs switching) = 304mW + 151mW = 455mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.455W * 66.6C/W = 115C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
6A. T
HERMAL
R
ESISTANCE


JA
FOR
20-
PIN
TSSOP, F
ORCED
C
ONVECTION


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2C/W
65.7C/W
57.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2C/W
39.7C/W
36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
6B. T
HERMAL
R
ESISTANCE


JA
FOR
20-
PIN
SOIC, F
ORCED
C
ONVECTION
85314AGI-11
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REV. C MAY 24, 2005
13
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in
Figure 6.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
1.0V
(V
CC_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CC_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
6. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
14
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS85314I-11 is: 674
Compatible to part number MC100LVEP14
T
ABLE
7A.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
20 L
EAD
TSSOP


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2C/W
65.7C/W
57.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2C/W
39.7C/W
36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
7B.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
20 L
EAD
SOIC


JA
by Velocity (Linear Feet per Minute)
85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
15
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
20 L
EAD
TSSOP
T
ABLE
8A. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
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85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
16
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- M S
UFFIX
FOR
20 L
EAD
TSSOP
T
ABLE
8B. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-013, MO-119
L
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85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
17
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
85314AGI-11
www.icst.com/products/hiperclocks.html
REV. C MAY 24, 2005
18
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
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