Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply 3.3V or 2.5V DC Characteristics
- LVCMOS 3.3V DC Characteristics
- LVCMOS 2.5V DC Characteristics
- LVPECL 3.3V or 2.5V DC Characteristics
- 3.3V AC Characteristics
- 2.5V AC Characteristics
- Parameter Measurement Information
- 3.3V Core/3.3V Output Load AC Test Circuit Diagram
- 2.5V Core/2.5V Output Load AC Test Circuit Diagram
- Part-to-Part Skew Diagram
- Output Rise/Fall Time Diagram
- Propagation Delay Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Application Information
- Termination for 3.3V LVPECL Outputs
- Termination for 2.5V LVPECL Outputs
- Application Schematic Example
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
85320AMI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 25, 2004
1
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
G
ENERAL
D
ESCRIPTION
The ICS85320I is a LVCMOS / LVTTL-to-Differ-
ential 2.5V / 3.3V LVPECL translator and a mem-
ber of the HiPerClocksTM
family of High Perfor-
m a n c e C l o ck s S o l u t i o n s f r o m I C S. T h e
ICS85320I has a single ended clock input. The
single ended clock input accepts LVCMOS or LVTTL input
levels and translates them to 2.5V / 3.3V LVPECL levels. The
small outline 8-pin SOIC package makes this device ideal for
applications where space, high performance and low power
are important.
F
EATURES
1 differential 2.5V/3.3V LVPECL output
LVCMOS/LVTTL CLK input
CLK accepts the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 267MHz
Part-to-part skew: 275ps (maximum)
Additive phase jitter, RMS: 0.05ps (typical)
3.3V operating supply voltage
(operating range 3.135V to 3.465V)
2.5V operating supply voltage
(operating range 2.375V to 2.625V)
-40C to 85C ambient operating temperature
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS85320I
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
nc
Q
nQ
nc
1
2
3
4
Q
nQ
CLK
HiPerClockSTM
ICS
V
CC
CLK
nc
V
EE
8
7
6
5
85320AMI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 25, 2004
2
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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85320AMI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 25, 2004
3
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V5%
OR
2.5V5%, T
A
= -40C
TO
85C
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= -40C
TO
85C
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3D. LVPECL DC C
HARACTERISTICS
,
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CC
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OR
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= -40C
TO
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A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
112.7C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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T
ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 2.5V5%, T
A
= -40C
TO
85C
85320AMI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 25, 2004
4
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ABLE
4B. AC C
HARACTERISTICS
,
V
CC
= 2.5V5%, T
A
= -40C
TO
85C
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85320AMI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 25, 2004
5
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
A
DDITIVE
P
HASE
J
ITTER
Input/Output Additive Phase Jitter
@ 156.25MHz (12KHz to 20MHz)
= 0.05ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dBc/H
Z
85320AMI
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REV. A AUGUST 25, 2004
6
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
P
ART
-
TO
-P
ART
S
KEW
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.165V
V
EE
V
CC
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
P
ROPAGATION
D
ELAY
t
sk(o)
nQx
Qx
nQy
Qy
Part 1
Part 2
t
PD
CLK
nCLK
Q
nQ
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
Q
nQ
SCOPE
Qx
nQx
LVPECL
2V
-0.5V 0.125V
V
EE
V
CC
85320AMI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 25, 2004
7
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
A
PPLICATION
I
NFORMATION
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 1A and 1B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
3.3V
LVPECL O
UTPUTS
F
IGURE
1B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
1A. LVPECL O
UTPUT
T
ERMINATION
85320AMI
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REV. A AUGUST 25, 2004
8
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 2A and Figure 2B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very close to
ground level. The R3 in Figure 2B can be eliminated and the
termination is shown in
Figure 2C.
F
IGURE
2B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
F
IGURE
2A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
Zo = 50 Ohm
R1
250
+
-
2.5V
2,5V LVPECL
Driv er
R4
62.5
R3
250
Zo = 50 Ohm
2.5V
VCC=2.5V
R1
50
R3
18
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
VCC=2.5V
2.5V
R2
50
2,5V LVPECL
Driv er
VCC=2.5V
R1
50
R2
50
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
+
-
F
IGURE
2C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
85320AMI
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REV. A AUGUST 25, 2004
9
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
R1
50
(U1-8)
R4
133
R6
133
Optional Termination
R2
50
Clk_in
R7
82.5
Zo = 50 Ohm
C2
0.1uF
R3
50
R5
82.5
C1
10uf
Zo = 50 Ohm
VCC = 3.3V
Zo = 50 Ohm
Zo = 50 Ohm
VCC
VCC = 3.3V
+
-
U1
85320
1
2
3
4
8
7
6
5
nc
Q
nQ
nc
Vcc
Clk
nc
Vee
A
PPLICATION
S
CHEMATIC
E
XAMPLE
Figure 3 shows an example of ICS85320I application schematic.
In this example, the device is operated at V
CC
=3.3V. The
decoupling capacitor should be located as close as possible to
the power pin. For LVPECL output termination, only two termi-
F
IGURE
3. ICS85320I A
PPLICATION
S
CHEMATIC
E
XAMPLE
nations examples are shown in this schematic. For more termi-
nation approaches, please refer to the LVPECL Termination Ap-
plication Note.
85320AMI
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REV. A AUGUST 25, 2004
10
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85320I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85320I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 25mA = 86.6mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
Total Power
_MAX
(3.465V, with all outputs switching) = 86.6mW + 30.2mW = 116.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.117W * 103.3C/W = 97.1C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
JA
by Velocity (Linear Feet per Minute)
T
ABLE
5. T
HERMAL
R
ESISTANCE
JA
FOR
8-
PIN
SOIC, F
ORCED
C
ONVECTION
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
153.3C/W
128.5C/W
115.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7C/W
103.3C/W
97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85320AMI
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REV. A AUGUST 25, 2004
11
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 4.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
1.0V
(V
CCO_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
4. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
85320AMI
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REV. A AUGUST 25, 2004
12
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS85320I is: 269
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
SOIC
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
153.3C/W
128.5C/W
115.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7C/W
103.3C/W
97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85320AMI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 25, 2004
13
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
P
ACKAGE
O
UTLINE
- M S
UFFIX
FOR
8 L
EAD
SOIC
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-012
L
O
B
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Y
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r
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85320AMI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 25, 2004
14
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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