85322AM
www.icst.com/products/hiperclocks.html
REV. A JULY 31, 2001
1
Integrated
Circuit
Systems, Inc.
ICS85322
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
G
ENERAL
D
ESCRIPTION
The ICS85322 is a Dual LVCMOS / LVTTL-to-
Differential 2.5V / 3.3V LVPECL translator and a
member of the HiPerClocksTM family of High Per-
formance Clocks Solutions from ICS. The
ICS85322 has selectable single ended clock in-
puts. The single ended clock input accepts LVCMOS or LVTTL
input levels and translate them to 2.5V / 3.3V LVPECL levels.
The small outline 8-pin SOIC package makes this device ideal
for applications where space, high performance and low power
are important.
F
EATURES
2 differential 2.5V/3.3V LVPECL outputs
Selectable CLK0, CLK1 LVCMOS clock inputs
CLK0 and CLK1 can accepts the following input levels:
LVCMOS or LVTTL
Maximum output frequency up to 267MHz
Part-to-part skew: 150ps (maximum)
3.3V operating supply voltage
(operating range 3.135V to 3.465V)
2.5V operating supply voltage
(operating range 2.375V to 2.625V)
0C to 70C ambient operating temperature
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS85322
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
Q0
nQ0
Q1
nQ1
CLK0
CLK1
HiPerClockSTM
,&6
V
CC
CLK0
CLK1
V
EE
8
7
6
5
85322AM
www.icst.com/products/hiperclocks.html
REV. A JULY 31, 2001
2
Integrated
Circuit
Systems, Inc.
ICS85322
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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85322AM
www.icst.com/products/hiperclocks.html
REV. A JULY 31, 2001
3
Integrated
Circuit
Systems, Inc.
ICS85322
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, V
O
-0.5V to V
CC
+ 0.5V
Package Thermal Impedance,
JA
112.7C/W (0lfpm)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= 0C
TO
70C
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,
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85322AM
www.icst.com/products/hiperclocks.html
REV. A JULY 31, 2001
4
Integrated
Circuit
Systems, Inc.
ICS85322
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ABLE
4A. AC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= 0C
TO
70C
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85322AM
www.icst.com/products/hiperclocks.html
REV. A JULY 31, 2001
5
Integrated
Circuit
Systems, Inc.
ICS85322
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ABLE
3D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.5V5%, T
A
= 0C
TO
70C
T
ABLE
3E. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 2.5V5%, T
A
= 0C
TO
70C
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-
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T
ABLE
3F. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.5V5%, T
A
= 0C
TO
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85322AM
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REV. A JULY 31, 2001
6
Integrated
Circuit
Systems, Inc.
ICS85322
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
F
IGURE
1B - 2.5V O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
V
CC
= 2V
V
CC
V
EE
= -0.5V 0.125V
F
IGURE
1A - 3.3V O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
V
CC
= 2V
V
CC
V
EE
= -1.3V 0.135V
85322AM
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REV. A JULY 31, 2001
7
Integrated
Circuit
Systems, Inc.
ICS85322
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
F
IGURE
2 - P
ART
-
TO
-P
ART
S
KEW
Qx
nQx
Qy
nQy
PART 1
PART 2
tsk(pp)
F
IGURE
3 - I
NPUT
AND
O
UTPUT
R
ISE
AND
F
ALL
T
IME
Clock Inputs
and Outputs
20%
80%
20%
80%
t
R
t
F
V
S W I N G
85322AM
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REV. A JULY 31, 2001
8
Integrated
Circuit
Systems, Inc.
ICS85322
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
F
IGURE
4 - P
ROPAGATION
D
ELAY
F
IGURE
5 - odc & t
P
ERIOD
CLK0, CLK1
Q0 - Q1
nQ0 - nQ1
t
PD
V
CC
/2
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
CLK0, CLK1, Q0, Q1
nQ0, nQ1
85322AM
www.icst.com/products/hiperclocks.html
REV. A JULY 31, 2001
9
Integrated
Circuit
Systems, Inc.
ICS85322
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85322.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85322 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 25mA = 86.6mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power
_MAX
(3.465V, with all outputs switching) = 86.6mW + 60.4mW = 147mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used
. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.147W * 103.3C/W = 85.2C. This is well below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 153.3C/W
128.5C/W
115.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7C/W
103.3C/W
97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 5. Thermal Resistance
q
JA
for 8-pin SOIC, Forced Convection
85322AM
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REV. A JULY 31, 2001
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Integrated
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Systems, Inc.
ICS85322
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
)
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
)
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
1.0V
Using V
CC_MAX
= 3.465, this results in V
OH_MAX
= 2.465V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
Using V
CC_MAX
= 3.465, this results in V
OL_MAX
= 1.765V
Pd_H = [(2.465V - (3.465V - 2V))/50
] * (3.465V - 2.465V) = 20mW
Pd_L = [(1.765V - (3.465V - 2V))/50
] * (3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
6 - LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
85322AM
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REV. A JULY 31, 2001
11
Integrated
Circuit
Systems, Inc.
ICS85322
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS85322 is: 269
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 153.3C/W
128.5C/W
115.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7C/W
103.3C/W
97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85322AM
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REV. A JULY 31, 2001
12
Integrated
Circuit
Systems, Inc.
ICS85322
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
P
ACKAGE
O
UTLINE
- M S
UFFIX
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-012
L
O
B
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e
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85322AM
www.icst.com/products/hiperclocks.html
REV. A JULY 31, 2001
13
Integrated
Circuit
Systems, Inc.
ICS85322
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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