Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- LVCMOS 3.3V DC Characteristics
- LVPECL 3.3V DC Characteristics
- 3.3V AC Characteristics
- Power Supply 2.5V DC Characteristics
- LVCMOS 2.5V DC Characteristics
- LVPECL 2.5V DC Characteristics
- 2.5V AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- 2.5V Output Load AC Test Circuit Diagram
- Part-to-Part Skew Diagram
- Propagation Delay Diagram
- Output Rise/Fall Time Diagram
- Output Duty Cyle/Pulse Width/Period Diagram
- Application Information
- Termination for 3.3V LVPECL Outputs
- Termination for 2.5V LVPECL Outputs
- Power Consideraitons
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
85322AMI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 7, 2003
1
Integrated
Circuit
Systems, Inc.
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
G
ENERAL
D
ESCRIPTION
The ICS85322I is a Dual LVCMOS / LVTTL-to-
Differential 2.5V / 3.3V LVPECL translator and a
member of the HiPerClocksTM family of High Per-
for mance Clocks Solutions from ICS. The
ICS85322I has selectable single ended clock in-
puts. The single ended clock input accepts LVCMOS or LVTTL
input levels and translate them to 2.5V / 3.3V LVPECL levels.
The small outline 8-pin SOIC package makes this device ideal
for applications where space, high performance and low power
are important.
F
EATURES
2 differential 2.5V/3.3V LVPECL outputs
Selectable CLK0, CLK1 LVCMOS/LVTTL clock inputs
CLK0 and CLK1 can accepts the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 267MHz
Part-to-part skew: 250ps (maximum)
3.3V operating supply voltage
(operating range 3.135V to 3.465V)
2.5V operating supply voltage
(operating range 2.375V to 2.625V)
-40C to 85C ambient operating temperature
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS85322I
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
Q0
nQ0
Q1
nQ1
CLK0
CLK1
HiPerClockSTM
ICS
V
CC
CLK0
CLK1
V
EE
8
7
6
5
85322AMI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 7, 2003
2
Integrated
Circuit
Systems, Inc.
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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85322AMI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 7, 2003
3
Integrated
Circuit
Systems, Inc.
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= -40C
TO
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,
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A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
112.7C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. AC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= -40C
TO
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85322AMI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 7, 2003
4
Integrated
Circuit
Systems, Inc.
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ABLE
3D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.5V5%, T
A
= -40C
TO
85C
T
ABLE
3E. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 2.5V5%, T
A
= -40C
TO
85C
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=
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1
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T
ABLE
3F. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.5V5%, T
A
= -40C
TO
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85322AMI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 7, 2003
5
Integrated
Circuit
Systems, Inc.
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
P
ART
-
TO
-P
ART
S
KEW
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
t
PD
P
ROPAGATION
D
ELAY
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
-1.3V 0.165V
t
sk(o)
nQx
Qx
nQy
Qy
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
Q0, Q1
nQ0, nQ1
CLK0,
CLK1
Q0, Q1
nQ0, nQ1
SCOPE
Qx
nQx
LVPECL
2V
-0.5V 0.125V
PART 1
PART 2
V
CC
V
EE
V
CC
V
EE
85322AMI
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REV. B OCTOBER 7, 2003
6
Integrated
Circuit
Systems, Inc.
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
A
PPLICATION
I
NFORMATION
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
(V
OH
+ V
OL
/ V
CC
2) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 1A and 1B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
3.3V LVPECL O
UTPUTS
F
IGURE
1B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
1A. LVPECL O
UTPUT
T
ERMINATION
85322AMI
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REV. B OCTOBER 7, 2003
7
Integrated
Circuit
Systems, Inc.
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 2A and Figure 2B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very close to
ground level. The R3 in Figure 2B can be eliminated and the
termination is shown in
Figure 2C.
F
IGURE
2C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driv er
F
IGURE
2B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driv er
Zo = 50 Ohm
+
-
2.5V
F
IGURE
2A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driv er
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
85322AMI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 7, 2003
8
Integrated
Circuit
Systems, Inc.
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85322I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85322I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 25mA = 86.6mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power
_MAX
(3.465V, with all outputs switching) = 86.6mW + 60.4mW = 147mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.147W * 103.3C/W = 100.2C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
153.3C/W
128.5C/W
115.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7C/W
103.3C/W
97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
5. T
HERMAL
R
ESISTANCE
JA
FOR
8-
PIN
SOIC, F
ORCED
C
ONVECTION
85322AMI
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REV. B OCTOBER 7, 2003
9
Integrated
Circuit
Systems, Inc.
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 3.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
1.0V
(V
CC_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CC_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
3. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
85322AMI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 7, 2003
10
Integrated
Circuit
Systems, Inc.
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS85322I is: 269
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
SOIC
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
153.3C/W
128.5C/W
115.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7C/W
103.3C/W
97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85322AMI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 7, 2003
11
Integrated
Circuit
Systems, Inc.
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
P
ACKAGE
O
UTLINE
- M S
UFFIX
FOR
8 L
EAD
SOIC
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-012
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85322AMI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 7, 2003
12
Integrated
Circuit
Systems, Inc.
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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85322AMI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 7, 2003
13
Integrated
Circuit
Systems, Inc.
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
E
E
H
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