Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- A Typical Application for the ICS85354
- Mode 1, 100BaseX Connected to SFP
- Mode 2, 1000BaseX Connected to SFP
- Pin Descriptions
- Pin Characteristics
- Control Input Funtion Table, Bank A
- Control Input Funtion Table, Bank B
- Absolute Maximum Ratings
- Power Supply DC Chararcteristics
- LVCMOS DC Chararcteristics
- LVPECL DC Chararcteristics
- ECL DC Chararcteristics
- AC Chararcteristics
- Parameter Measurement Information
- Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Part-to-Part Skew Diagram
- Propagation Delay Diagram
- Output Rise/Fall Time Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Termination for 3.3V LVPECL Outputs
- Termination for 2.5V LVPECL Outputs
- Differential Clock Input Interface
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
1
Integrated
Circuit
Systems, Inc.
ICS85354
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVPECL/ECL M
ULTIPLEXER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS85354 is a 2:1/1:2 Multiplexer and a mem-
ber of the HiPerClockS
TM
family of high perfor-
mance clock solutions from ICS. The 2:1 Multiplexer
allows one of 2 inputs to be selected onto one out-
put pin and the 1:2 MUX switches one input to one
of two outputs. This device may be useful for multiplexing multi-
rate Ethernet Phys which have 100Mbit and 1000Mbit transmit/
receive pairs onto an optical SFP module which has a single
trasmit/receive pair. Please refer to the Application Block dia-
gram on page 2 of the data sheet.
The ICS85354 is optimized for applications requiring very high
performance and has a maximum operating frequency in excess
of 2GHz. The device is packaged in a small, 3mm x 3mm VFQFN
package, making it ideal for use on space-constrained boards.
F
EATURES
Dual 2:1/1:2 MUX
3 LVPECL outputs
3 differential clock inputs
CLKx pair can accept the following differential input levels:
LVPECL, LVDS, CML
Maximum output frequency: 3GHz
Part-to-part skew: 85ps (typical)
Additive jitter, RMS: 0.03ps (typical)
Propagation delay: 330ps (typical)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.465V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.465V to -2.375V
-40C to 85C ambient operating temperature
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
HiPerClockSTM
ICS
ICS85354
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
QB0
nQB0
QB1
nQB1
CLKA0
nCLKA0
CLKA1
nCLKA1
CLKB
nCLKB
CLK_SELB
V
EE
QA
nQA
CLK_SELA
V
CC
1
2
3
4
12
11
10
9
5 6 7 8
16 15 14 13
0
1
CLK_SELA
CLKA0
nCLKA0
CLKA1
nCLKA1
CLKB
nCLKB
CLK_SELB
QA
nQA
QB0
nQB0
QB1
nQB1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
2
Integrated
Circuit
Systems, Inc.
ICS85354
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVPECL/ECL M
ULTIPLEXER
PRELIMINARY
A T
YPICAL
A
PPLICATION
FOR
THE
ICS85354
Used to connect a multi-rate PHY with the Tx/Rx pins of an
SFP Module.
Problem Addressed: How to mape the 2 Tx/Rx pairs of the
multi-rate PHY to the single Tx/Rx pair on the SFP Module.
100BaseFX
1000BaseX
M
ULTI
-R
ATE
PHY
SFP M
ODULE
Tx
Rx
Tx
Rx
Rx
Tx
?
Bold red lines are active connections highlighting the
signal path.
M
ODE
1, 100B
ASE
X C
ONNECTED
TO
SFP
All lines are differential pairs, but drawn as single-ended to
simplify the drawing.
M
ULTI
-R
ATE
PHY
SFP M
ODULE
100BaseFX
1000BaseX
Tx
Rx
Tx
Rx
Rx
Tx
0
1
CLK_SELA = 0
CLKA0
CLKA1
QB0
QB1
QA
CLKB
CLK_SELB = 0
ICS85354
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
3
Integrated
Circuit
Systems, Inc.
ICS85354
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVPECL/ECL M
ULTIPLEXER
PRELIMINARY
Bold red lines are active connections highlighting
the signal path.
M
ODE
2, 1000B
ASE
X C
ONNECTED
TO
SFP
All lines are differential pairs, but drawn as single-ended to
simplify the drawing.
M
ULTI
-R
ATE
PHY
SFP M
ODULE
100BaseFX
1000BaseX
Tx
Rx
Tx
Rx
Rx
Tx
0
1
CLK_SELA = 1
CLKA0
CLKA1
QB0
QB1
QA
CLKB
CLK_SELB = 1
ICS85354
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
4
Integrated
Circuit
Systems, Inc.
ICS85354
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVPECL/ECL M
ULTIPLEXER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
r
e
b
m
u
N
e
m
a
N
e
p
y
T
n
o
i
t
p
i
r
c
s
e
D
2
,
1
0
B
Q
n
,
0
B
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
C
E
/
L
C
E
P
V
L
.
r
i
a
p
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
4
,
3
1
B
Q
n
,
1
B
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
C
E
/
L
C
E
P
V
L
.
r
i
a
p
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
5
B
K
L
C
t
u
p
n
I
n
w
o
d
ll
u
P
.
t
u
p
n
i
k
c
o
l
c
l
a
i
t
n
e
r
e
f
f
i
d
L
C
E
/
L
C
E
P
V
L
g
n
i
t
r
e
v
n
i
-
n
o
N
6
B
K
L
C
n
t
u
p
n
I
/
p
u
ll
u
P
n
w
o
d
ll
u
P
V
.
t
u
p
n
i
k
c
o
l
c
L
C
E
P
V
L
l
a
i
t
n
e
r
e
f
f
i
d
g
n
i
t
r
e
v
n
I
C
C
.
g
n
i
t
a
o
l
f
t
f
e
l
n
e
h
w
t
l
u
a
f
e
d
2
/
7
B
L
E
S
_
K
L
C
t
u
p
n
I
n
w
o
d
ll
u
P
1
B
Q
n
,
1
B
Q
s
t
c
e
l
e
s
,
H
G
I
H
n
e
h
W
.
s
t
u
p
t
u
o
x
B
Q
r
o
f
n
i
p
t
c
e
l
e
s
k
c
o
l
C
.
s
t
u
p
t
u
o
0
B
Q
n
,
0
B
Q
s
t
c
e
l
e
s
,
W
O
L
n
e
h
W
.
s
t
u
p
t
u
o
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
8
V
E
E
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
e
v
i
t
a
g
e
N
9
1
A
K
L
C
n
t
u
p
n
I
/
p
u
ll
u
P
n
w
o
d
ll
u
P
V
.
t
u
p
n
i
k
c
o
l
c
L
C
E
P
V
L
l
a
i
t
n
e
r
e
f
f
i
d
g
n
i
t
r
e
v
n
I
C
C
.
g
n
i
t
a
o
l
f
t
f
e
l
n
e
h
w
t
l
u
a
f
e
d
2
/
0
1
1
A
K
L
C
t
u
p
n
I
n
w
o
d
ll
u
P
.
t
u
p
n
i
k
c
o
l
c
l
a
i
t
n
e
r
e
f
f
i
d
L
C
E
P
V
L
g
n
i
t
r
e
v
n
i
-
n
o
N
1
1
0
A
K
L
C
n
t
u
p
n
I
/
p
u
ll
u
P
n
w
o
d
ll
u
P
V
.
t
u
p
n
i
k
c
o
l
c
L
C
E
P
V
L
l
a
i
t
n
e
r
e
f
f
i
d
g
n
i
t
r
e
v
n
I
C
C
.
g
n
i
t
a
o
l
f
t
f
e
l
n
e
h
w
t
l
u
a
f
e
d
2
/
2
1
0
A
K
L
C
t
u
p
n
I
n
w
o
d
ll
u
P
.
t
u
p
n
i
k
c
o
l
c
l
a
i
t
n
e
r
e
f
f
i
d
L
C
E
P
V
L
g
n
i
t
r
e
v
n
i
-
n
o
N
3
1
V
C
C
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
e
v
i
t
i
s
o
P
4
1
A
L
E
S
_
K
L
C
t
u
p
n
I
n
w
o
d
ll
u
P
.
t
u
p
t
u
o
A
Q
s
t
c
e
l
e
s
,
H
G
I
H
n
e
h
W
.
s
t
u
p
t
u
o
A
Q
r
o
f
n
i
p
t
c
e
l
e
s
k
c
o
l
C
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
t
u
p
t
u
o
A
Q
n
s
t
c
e
l
e
s
,
W
O
L
n
e
h
W
6
1
,
5
1
A
Q
,
A
Q
n
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
C
E
/
L
C
E
P
V
L
.
r
i
a
p
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
:
E
T
O
N
p
u
ll
u
P
d
n
a
n
w
o
d
ll
u
P
.
s
e
u
l
a
v
l
a
c
i
p
y
t
r
o
f
,
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
n
i
P
,
2
e
l
b
a
T
e
e
S
.
s
r
o
t
s
i
s
e
r
t
u
p
n
i
l
a
n
r
e
t
n
i
o
t
r
e
f
e
r
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
R
N
W
O
D
L
L
U
P
r
o
t
s
i
s
e
R
n
w
o
d
ll
u
P
t
u
p
n
I
5
.
7
3
K
R
2
/
C
C
V
s
r
o
t
s
i
s
e
R
n
w
o
d
ll
u
P
/
p
u
ll
u
P
5
.
7
3
K
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
, B
ANK
A
A
k
n
a
B
s
t
u
p
n
I
l
o
r
t
n
o
C
s
t
u
p
t
u
O
A
L
E
S
_
K
L
C
A
Q
n
,
A
Q
0
0
A
K
L
C
n
,
0
A
K
L
C
s
t
c
e
l
e
S
1
1
A
K
L
C
n
,
1
A
K
L
C
s
t
c
e
l
e
S
B
k
n
a
B
s
t
u
p
n
I
l
o
r
t
n
o
C
s
t
u
p
t
u
O
B
L
E
S
_
K
L
C
0
B
Q
n
,
0
B
Q
1
B
Q
n
,
1
B
Q
0
t
u
p
n
i
B
K
L
C
s
w
o
ll
o
F
w
o
L
1
w
o
L
t
u
p
n
i
B
K
L
C
s
w
o
ll
o
F
T
ABLE
3B. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
, B
ANK
B
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
5
Integrated
Circuit
Systems, Inc.
ICS85354
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVPECL/ECL M
ULTIPLEXER
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.465V, V
EE
= 0V
OR
V
CC
= 0V, V
EE
= -3.465V
TO
-2.375V
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
C
C
e
g
a
t
l
o
V
y
l
p
p
u
S
e
v
i
t
i
s
o
P
5
3
1
.
3
3
.
3
5
6
4
.
3
V
5
7
3
.
2
5
.
2
5
2
6
.
2
V
I
E
E
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
8
3
A
m
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V (LVPECL mode, V
EE
= 0)
Negative Supply Voltage, V
EE
-4.6V (ECL mode, V
CC
= 0)
Inputs, V
I
(LVPECL mode)
-0.5V to V
CC
+ 0.5 V
Inputs, V
I
(ECL mode)
0.5V to V
EE
- 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Operating Temperature Range, TA -40C to +85C
Storage Temperature, T
STG
-65C to 150C
Package Thermal Impedance,
JA
51.5C/W (0 lfpm)
(Junction-to-Ambient)
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
I
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
x
L
E
S
_
K
L
C
V
C
C
V
3
.
3
r
o
V
5
.
2
=
2
V
C
C
3
.
0
+
V
V
L
I
e
g
a
t
l
o
V
w
o
L
t
u
p
n
I
x
L
E
S
_
K
L
C
V
C
C
V
3
.
3
r
o
V
5
.
2
=
0
8
.
0
V
I
H
I
t
n
e
r
r
u
C
h
g
i
H
t
u
p
n
I
,
A
L
E
S
_
K
L
C
B
L
E
S
_
K
L
C
V
C
C
V
=
N
I
,
V
5
6
4
.
3
=
V
C
C
V
=
N
I
V
5
2
6
.
2
=
0
5
1
A
I
L
I
t
n
e
r
r
u
C
w
o
L
t
u
p
n
I
,
A
L
E
S
_
K
L
C
B
L
E
S
_
K
L
C
V
C
C
5
6
4
.
3
=
V
,
V
5
2
6
.
2
N
I
V
0
=
0
5
1
-
A
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.465V
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
6
Integrated
Circuit
Systems, Inc.
ICS85354
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVPECL/ECL M
ULTIPLEXER
PRELIMINARY
T
ABLE
4D. ECL DC C
HARACTERISTICS
,
V
EE
= -3.465V
TO
-2.375V, V
CC
= 0V
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
C
0
4
-
C
5
2
C
5
8
s
t
i
n
U
n
i
M
p
y
T
x
a
M
n
i
M
p
y
T
x
a
M
n
i
M
p
y
T
x
a
M
V
H
O
1
E
T
O
N
;
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
5
2
1
.
1
-
5
2
0
.
1
-
2
9
.
0
-
5
7
0
.
1
-
5
0
0
.
1
-
3
9
.
0
-
5
0
0
.
1
-
7
9
.
0
-
5
3
9
.
0
-
V
V
L
O
1
E
T
O
N
;
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
5
9
8
.
1
-
5
5
7
.
1
-
2
6
.
1
-
5
7
8
.
1
-
8
7
.
1
-
5
8
6
.
1
-
6
8
.
1
-
5
6
7
.
1
-
7
6
.
1
-
V
V
P
P
e
g
a
t
l
o
V
t
u
p
n
I
k
a
e
P
-
o
t
-
k
a
e
P
0
5
1
0
0
8
0
0
2
1
0
5
1
0
0
8
0
0
2
1
0
5
1
0
0
8
0
0
2
1
m
V
V
R
M
C
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
3
,
2
E
T
O
N
;
e
g
n
a
R
e
d
o
M
n
o
m
m
o
C
V
E
E
V
2
.
1
+
V
C
C
V
E
E
V
2
.
1
+
V
C
C
V
E
E
V
2
.
1
+
V
C
C
V
I
H
I
t
u
p
n
I
t
n
e
r
r
u
C
h
g
i
H
B
K
L
C
,
x
A
K
L
C
B
K
L
C
n
,
x
A
K
L
C
n
0
5
1
0
5
1
0
5
1
A
I
L
I
t
u
p
n
I
t
n
e
r
r
u
C
w
o
L
B
K
L
C
,
x
A
K
L
C
0
1
-
0
1
-
0
1
-
A
B
K
L
C
n
,
x
A
K
L
C
n
0
5
1
-
0
5
1
-
0
5
1
-
A
V
h
t
i
w
1
:
1
y
r
a
v
s
r
e
t
e
m
a
r
a
p
t
u
p
t
u
o
d
n
a
t
u
p
n
I
C
C
.
0
5
h
t
i
w
d
e
t
a
n
i
m
r
e
t
s
t
u
p
t
u
O
:
1
E
T
O
N
V
o
t
C
C
.
V
2
-
V
s
a
d
e
n
i
f
e
d
s
i
e
g
a
t
l
o
v
e
d
o
m
n
o
m
m
o
C
:
2
E
T
O
N
H
I
.
B
K
L
C
n
,
B
K
L
C
d
n
a
x
A
K
L
C
n
,
x
A
K
L
C
r
o
f
e
g
a
t
l
o
v
t
u
p
n
i
m
u
m
i
x
a
m
e
h
t
,
s
n
o
i
t
a
c
il
p
p
a
d
e
d
n
e
-
e
l
g
n
i
s
r
o
F
:
3
E
T
O
N
V
s
i
C
C
.
V
3
.
0
+
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V, V
EE
= 0V
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
C
0
4
-
C
5
2
C
5
8
s
t
i
n
U
n
i
M
p
y
T
x
a
M
n
i
M
p
y
T
x
a
M
n
i
M
p
y
T
x
a
M
V
H
O
;
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
1
E
T
O
N
V
C
C
5
2
1
.
1
-
V
C
C
5
2
0
.
1
-
V
C
C
2
9
.
0
-
V
C
C
5
7
0
.
1
-
V
C
C
5
0
0
.
1
-
V
C
C
-
3
9
.
0
V
C
C
5
0
0
.
1
-
V
C
C
7
9
.
0
-
V
C
C
5
3
9
.
0
-
V
V
L
O
;
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
1
E
T
O
N
V
C
C
5
9
8
.
1
-
V
C
C
5
5
7
.
1
-
V
C
C
2
6
.
1
-
V
C
C
5
7
8
.
1
-
V
C
C
8
7
.
1
-
V
C
C
5
8
6
.
1
-
V
C
C
6
8
.
1
-
V
C
C
5
6
7
.
1
-
V
C
C
7
6
.
1
-
V
V
P
P
k
a
e
P
-
o
t
-
k
a
e
P
e
g
a
t
l
o
V
t
u
p
n
I
0
5
1
0
0
8
0
0
2
1
0
5
1
0
0
8
0
0
2
1
0
5
1
0
0
8
0
0
2
1
V
m
V
R
M
C
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
;
e
g
n
a
R
e
d
o
M
n
o
m
m
o
C
3
,
2
E
T
O
N
2
.
1
V
C
C
2
.
1
V
C
C
2
.
1
V
C
C
V
I
H
I
t
u
p
n
I
t
n
e
r
r
u
C
h
g
i
H
,
x
A
K
L
C
B
K
L
C
,
x
A
K
L
C
n
B
K
L
C
n
0
5
1
0
5
1
0
5
1
A
I
L
I
t
u
p
n
I
t
n
e
r
r
u
C
w
o
L
,
x
A
K
L
C
B
K
L
C
0
1
-
0
1
-
0
1
-
A
,
x
A
K
L
C
n
B
K
L
C
n
0
5
1
-
0
5
1
-
0
5
1
-
A
V
h
t
i
w
1
:
1
y
r
a
v
s
r
e
t
e
m
a
r
a
p
t
u
p
t
u
o
d
n
a
t
u
p
n
I
C
C
V
.
C
C
.
V
5
2
9
.
0
-
o
t
V
5
6
1
.
0
+
y
r
a
v
n
a
c
0
5
h
t
i
w
d
e
t
a
n
i
m
r
e
t
s
t
u
p
t
u
O
:
1
E
T
O
N
V
o
t
C
C
.
V
2
-
V
s
a
d
e
n
i
f
e
d
s
i
e
g
a
t
l
o
v
e
d
o
m
n
o
m
m
o
C
:
2
E
T
O
N
H
I
.
B
K
L
C
n
,
B
K
L
C
d
n
a
x
A
K
L
C
n
,
x
A
K
L
C
r
o
f
e
g
a
t
l
o
v
t
u
p
n
i
m
u
m
i
x
a
m
e
h
t
,
s
n
o
i
t
a
c
il
p
p
a
d
e
d
n
e
-
e
l
g
n
i
s
r
o
F
:
3
E
T
O
N
V
s
i
C
C
.
V
3
.
0
+
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
7
Integrated
Circuit
Systems, Inc.
ICS85354
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVPECL/ECL M
ULTIPLEXER
PRELIMINARY
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.465V, V
EE
= 0V
OR
V
CC
= 0V, V
EE
= -3.465V
TO
-2.375V
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
X
A
M
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
3
z
H
G
t
D
P
1
E
T
O
N
;
y
a
l
e
D
n
o
i
t
a
g
a
p
o
r
P
0
3
3
s
p
t
)
p
p
(
k
s
4
,
3
E
T
O
N
;
w
e
k
S
t
r
a
P
-
o
t
-
t
r
a
P
5
8
s
p
t t
ij
;
S
M
R
,
r
e
t
t
i
J
e
s
a
h
P
e
v
i
t
i
d
d
A
r
e
f
f
u
B
n
o
i
t
c
e
s
r
e
t
t
i
J
e
s
a
h
P
e
v
i
t
i
d
d
A
o
t
r
e
f
e
r
3
0
.
0
s
p
n
o
i
t
a
l
o
s
I
X
U
M
5
5
B
d
t
R
/t
F
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
7
1
s
p
d
e
r
u
s
a
e
m
e
r
a
s
r
e
t
e
m
a
r
a
p
ll
A
.
d
e
t
o
n
e
s
i
w
r
e
h
t
o
s
s
e
l
n
u
z
H
G
1
.
t
n
i
o
p
g
n
i
s
s
o
r
c
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
d
e
h
t
o
t
t
n
i
o
p
g
n
i
s
s
o
r
c
t
u
p
n
i
l
a
i
t
n
e
r
e
f
f
i
d
e
h
t
m
o
r
f
d
e
r
u
s
a
e
M
:
1
E
T
O
N
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
d
n
a
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
2
E
T
O
N
.
s
t
n
i
o
p
s
s
o
r
c
l
a
i
t
n
e
r
e
f
f
i
d
t
u
p
t
u
o
e
h
t
t
a
d
e
r
u
s
a
e
M
s
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
g
n
i
t
a
r
e
p
o
s
e
c
i
v
e
d
t
n
e
r
e
f
f
i
d
n
o
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
3
E
T
O
N
d
e
r
u
s
a
e
m
e
r
a
s
t
u
p
t
u
o
e
h
t
,
e
c
i
v
e
d
h
c
a
e
n
o
s
t
u
p
n
i
f
o
e
p
y
t
e
m
a
s
e
h
t
g
n
i
s
U
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
d
n
a
.
s
t
n
i
o
p
s
s
o
r
c
l
a
i
t
n
e
r
e
f
f
i
d
e
h
t
t
a
.
5
6
d
r
a
d
n
a
t
S
C
E
D
E
J
h
t
i
w
e
c
n
a
d
r
o
c
c
a
n
i
d
e
n
i
f
e
d
s
i
r
e
t
e
m
a
r
a
p
s
i
h
T
:
4
E
T
O
N
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
8
Integrated
Circuit
Systems, Inc.
ICS85354
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVPECL/ECL M
ULTIPLEXER
PRELIMINARY
O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
P
ROPAGATION
D
ELAY
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
R
ISE
/F
ALL
T
IME
V
CMR
Cross Points
V
PP
V
EE
nCLKA0, nCLKA1
nCLKB
V
CC
CLKA0, CLKA1
CLKB
SCOPE
Qx
nQx
LVPECL
2V
-0.375V to -1.465V
tsk(pp)
nQx
Qx
nQy
Qy
PART 1
PART 2
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
t
PD
nCLKA0,
nCLKA1
nCLKB
QA,
QB0,
QB1
nQA,
nQB0,
nQB1
CLKA0,
CLKA1
CLKB
V
CC
V
EE
P
ARAMETER
M
EASUREMENT
I
NFORMATION
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
9
Integrated
Circuit
Systems, Inc.
ICS85354
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVPECL/ECL M
ULTIPLEXER
PRELIMINARY
A
PPLICATION
I
NFORMATION
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
3.3V LVPECL O
UTPUTS
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLKx
nCLKx
VCC
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
10
Integrated
Circuit
Systems, Inc.
ICS85354
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVPECL/ECL M
ULTIPLEXER
PRELIMINARY
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very close to
ground level. The R3 in Figure 3B can be eliminated and the
termination is shown in
Figure 3C.
F
IGURE
3C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driv er
F
IGURE
3B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driv er
Zo = 50 Ohm
+
-
2.5V
F
IGURE
3A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driv er
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
11
Integrated
Circuit
Systems, Inc.
ICS85354
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVPECL/ECL M
ULTIPLEXER
PRELIMINARY
F
IGURE
4C. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
4B. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
4D. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements.
Figures 4A to 4E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
4A. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 4A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
F
IGURE
4E. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
12
Integrated
Circuit
Systems, Inc.
ICS85354
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVPECL/ECL M
ULTIPLEXER
PRELIMINARY
JA
by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5C/W
T
ABLE
6. T
HERMAL
R
ESISTANCE
JA
FOR
16-
PIN
VFQFN, F
ORCED
C
ONVECTION
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85354.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85354 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 38mA = 131.7mW
Power (outputs)
MAX
= 27.83mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 27.83mW = 111.3mW
Total Power
_MAX
(3.465, with all outputs switching) = 131.7mW + 111.3mW = 243mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.243W * 51.5C/W = 97.5C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
13
Integrated
Circuit
Systems, Inc.
ICS85354
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVPECL/ECL M
ULTIPLEXER
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
1.005V
(V
CC_MAX
- V
OH_MAX
) = 1.005
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.78V
(V
CC_MAX
- V
OL_MAX
) = 1.78V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 1.005V)/50
] * 1.005V = 20mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.78V)/50
] * 1.78V = 7.83mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 27.83mW
F
IGURE
5. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
VOUT
Q1
VCC - 2V
RL
50
VCC
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
14
Integrated
Circuit
Systems, Inc.
ICS85354
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVPECL/ECL M
ULTIPLEXER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS85354 is: 210
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
16 L
EAD
VFQFN
JA
by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5C/W
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
15
Integrated
Circuit
Systems, Inc.
ICS85354
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVPECL/ECL M
ULTIPLEXER
PRELIMINARY
P
ACKAGE
O
UTLINE
- K S
UFFIX
FOR
16 L
EAD
VFQFN
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-220
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
M
U
M
I
N
I
M
M
U
M
I
X
A
M
N
6
1
A
0
8
.
0
0
.
1
1
A
0
5
0
.
0
3
A
e
c
n
e
r
e
f
e
R
5
2
.
0
b
8
1
.
0
0
3
.
0
e
C
I
S
A
B
0
5
.
0
N
D
4
N
E
4
D
0
.
3
2
D
5
2
.
0
5
2
.
1
E
0
.
3
2
E
5
2
.
0
5
2
.
1
L
0
3
.
0
0
5
.
0
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
16
Integrated
Circuit
Systems, Inc.
ICS85354
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVPECL/ECL M
ULTIPLEXER
PRELIMINARY
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
r
e
b
m
u
N
r
e
d
r
O
/
t
r
a
P
g
n
i
k
r
a
M
e
g
a
k
c
a
P
t
n
u
o
C
e
r
u
t
a
r
e
p
m
e
T
K
A
4
5
3
5
8
S
C
I
A
4
5
3
N
F
Q
F
V
d
a
e
L
6
1
e
b
u
T
r
e
p
0
2
1
C
5
8
o
t
C
0
4
-
T
K
A
4
5
3
5
8
S
C
I
A
4
5
3
l
e
e
R
d
n
a
e
p
a
T
n
o
N
F
Q
F
V
d
a
e
L
6
1
0
0
5
3
C
5
8
o
t
C
0
4
-
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
PDF 
ZIP