85356AMI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 7, 2004
1
Integrated
Circuit
Systems, Inc.
ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS85356I
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm
M Package
Top View
G
ENERAL
D
ESCRIPTION
The ICS85356I is a dual 2:1 Differential-to-LVPECL
Multiplexer and is a member of the HiPerClockS
TM
family of High Performance Clock Solutions from
ICS. The device has both common select and indi-
vidual select inputs. When COM_SEL is logic High,
the CLKxx input pairs will be passed to the output. When
COM_SEL is logic Low, the output is determined by the setting
of the SEL0 pin for channel 0 and the SEL1 pin for Channel 1.
The differential input has a common mode range that can accept
most differential input types such as LVPECL, LVDS, LVHSTL,
SSTL, and HCSL. The ICS85356I can therefore be used as a
differential translator to translate almost any differential input type
to LVPECL. It can also be used in ECL mode by setting V
CC
=0V
and V
EE
to -3.0V to - 3.8V.
The ICS85356I adds negligible jitter to the input clock and can
operate at high frequencies in excess of 900MHz thus making
it ideal for use in demanding applications such as SONET,
Fibre Channel, 1 Gigabit/10 Gigabit Ethernet.
F
EATURES
High speed differential multiplexer.
The device can be configured as a 2:1 multiplexer
Dual 3.3V LVPECL outputs
Selectable differential CLKxx, nCLKxx inputs
CLKxx, nCLKxx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency: 900MHz (typical)
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nCLKxx input
Output skew: 75ps (typical)
Propagation delay: 1.15ns (typical)
LVPECL mode operating voltage supply range:
V
CC
= 3V to 3.8V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3V to -3.8V
-40C to 85C ambient operating temperature
Lead-Free package available
Compatible with MC100LVEL56
HiPerClockSTM
ICS
CLK0A
nCLK0A
CLK0B
nCLK0B
Q0
nQ0
SEL0
COM_SEL
SEL1
0
1
CLK1A
nCLK1A
CLK1B
nCLK1B
Q1
nQ1
0
1
ICS85356I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
G Package
Top View
CLK0A
nCLK0A
nc
CLK0B
nCLK0B
CLK1A
nCLK1A
nc
CLK1B
nCLK1B
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q0
nQ0
SEL0
COM_SEL
SEL1
V
CC
Q1
nQ1
V
EE
CLK0A
nCLK0A
nc
CLK0B
nCLK0B
CLK1A
nCLK1A
nc
CLK1B
nCLK1B
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q0
nQ0
SEL0
COM_SEL
SEL1
V
CC
Q1
nQ1
V
EE
85356AMI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 7, 2004
2
Integrated
Circuit
Systems, Inc.
ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
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85356AMI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 7, 2004
3
Integrated
Circuit
Systems, Inc.
ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V0.3V, T
A
= -40C
TO
85C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V0.3V, T
A
= -40C
TO
85C
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A
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
46.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
85356AMI
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REV. A OCTOBER 7, 2004
4
Integrated
Circuit
Systems, Inc.
ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V0.3V, T
A
= -40C
TO
85C
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:
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T
O
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T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V0.3V, T
A
= -40C
TO
85C
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o
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m
y
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-
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C
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0
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-
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L
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C
.
V
2
-
85356AMI
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REV. A OCTOBER 7, 2004
5
Integrated
Circuit
Systems, Inc.
ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
S
KEW
D
IFFERENTIAL
I
NPUT
L
EVEL
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
t
PD
P
ROPAGATION
D
ELAY
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
-1.3V 0.165V
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
Q0, Q1
nQ0, nQ1
V
CMR
Cross Points
V
PP
V
CC
V
EE
CLKxA,
CLKxB
nCLKxA,
nCLKxB
CLKxA,
CLKxB
nCLKxA,
nCLKxB
Q0, Q1
nQ0, nQ1
V
CC
V
EE
tsk(o)
nQx
Qx
nQy
Qy
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REV. A OCTOBER 7, 2004
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Systems, Inc.
ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
A
PPLICATION
I
NFORMATION
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLKx
nCLKx
VCC
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REV. A OCTOBER 7, 2004
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ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
F
IGURE
3C. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3B. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3D. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 3A to 3E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
3A. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
F
IGURE
3E. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
85356AMI
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REV. A OCTOBER 7, 2004
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Systems, Inc.
ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85356I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85356I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.6V * 40mA = 144mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power
_MAX
(3.6V, with all outputs switching) = 144mW + 60.4mW = 204.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used
. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.204W * 39.7C/W = 93.1C. This is well below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
JA
by Velocity (Linear Feet per Minute)
Table 6A. Thermal Resistance
JA
for 20-pin SOIC, Forced Convection
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2C/W
65.7C/W
57.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2C/W
39.7C/W
36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
JA
by Velocity (Linear Feet per Minute)
Table 6B. Thermal Resistance
JA
for 20-pin TSSOP, Forced Convection
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85356AMI
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REV. A OCTOBER 7, 2004
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2:1, D
IFFERENTIAL
-
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-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 4.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination voltage
of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
1.0V
(V
CC_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CC_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
Figure 4. LVPECL Driver Circuit and Termination
Q1
V
OUT
V
CC
RL = 50
V
CC
- 2V
85356AMI
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REV. A OCTOBER 7, 2004
10
Integrated
Circuit
Systems, Inc.
ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS85356I is: 446
T
ABLE
7A.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
20 L
EAD
SOIC
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2C/W
65.7C/W
57.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2C/W
39.7C/W
36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
JA
by Velocity (Linear Feet per Minute)
T
ABLE
7B.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
20 L
EAD
TSSOP
85356AMI
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REV. A OCTOBER 7, 2004
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ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
P
ACKAGE
O
UTLINE
- M S
UFFIX
FOR
20 L
EAD
SOIC
T
ABLE
8A. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS - 013, MO - 119
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
m
u
m
i
n
i
M
m
u
m
i
x
a
M
N
0
2
A
-
-
5
6
.
2
1
A
0
1
.
0
-
-
2
A
5
0
.
2
5
5
.
2
B
3
3
.
0
1
5
.
0
C
8
1
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0
2
3
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0
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0
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2
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3
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7
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7
2
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1
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0
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0
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5
6
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0
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h
5
2
.
0
5
7
.
0
L
0
4
.
0
7
2
.
1
0
8
85356AMI
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REV. A OCTOBER 7, 2004
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Integrated
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ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
20 L
EAD
TSSOP
T
ABLE
8B. P
ACKAGE
D
IMENSIONS
R
EFERENCE
D
OCUMENT
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95, MO-153
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85356AMI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 7, 2004
13
Integrated
Circuit
Systems, Inc.
ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
85356AMI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 7, 2004
14
Integrated
Circuit
Systems, Inc.
ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
T
E
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