Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Input Function Table
- CLK_EN Timing Diagram
- Clock Input Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- AC Characteristics
- Additive Phase Jitter
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- Part-to-Part Skew Diagram
- Output Skew Diagram
- Output Rise/Fall Time Diagram
- Propagation Delay Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Application Information
- Termination for LVPECL Outputs
- Schematic Example
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
8535AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2004
1
Integrated
Circuit
Systems, Inc.
ICS8535-21
L
OW
S
KEW
, 1-
TO
-2
LVCMOS/LVTTL-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8535-21 is a low skew, high performance
1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL fanout
buffer and a member of the HiPerClockSTM fam-
ily of High Performance Clock Solutions from
ICS. The ICS8535-21 has two single-ended clock
inputs. The single-ended clock input accepts LVCMOS or
LVTTL input levels and translate them to 3.3V LVPECL lev-
els. The clock enable is internally synchronized to eliminate
runt clock pulses on the output during asynchronous asser-
tion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8535-21 ideal for those applications demand-
ing well defined performance and repeatability.
F
EATURES
2 differential 3.3V LVPECL outputs
Selectable CLK0 or CLK1 inputs for redundant
and multiple frequency fanout applications
CLK0 or CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 266MHz
Translates LVCMOS and LVTTL levels to
3.3V LVPECL levels
Output skew: 20ps (maximum)
Part-to-part skew: 300ps (maximum)
Propagation delay: 1.6ns (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
3.3V operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
HiPerClockSTM
ICS
ICS8535-21
14-Lead TSSOP
4.4mm x 5.0mm x 0.92mm body package
G Package
Top View
CLK0
CLK1
Q0
nQ0
Q1
nQ1
0
1
CLK_EN
CLK_SEL
D
Q
LE
V
EE
CLK_EN
CLK_SEL
CLK0
V
EE
CLK1
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
Q0
nQ0
nc
Q1
nQ1
V
CC
8535AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2004
2
Integrated
Circuit
Systems, Inc.
ICS8535-21
L
OW
S
KEW
, 1-
TO
-2
LVCMOS/LVTTL-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
1. P
IN
D
ESCRIPTIONS
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8535AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2004
3
Integrated
Circuit
Systems, Inc.
ICS8535-21
L
OW
S
KEW
, 1-
TO
-2
LVCMOS/LVTTL-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
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F
IGURE
1. CLK_EN T
IMING
D
IAGRAM
Enabled
Disabled
CLK0, CLK1
CLK_EN
nQ0, nQ1
Q0, Q1
8535AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2004
4
Integrated
Circuit
Systems, Inc.
ICS8535-21
L
OW
S
KEW
, 1-
TO
-2
LVCMOS/LVTTL-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= 0C
TO
70C
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NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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o
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C
.
V
2
-
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
93.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
8535AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2004
5
Integrated
Circuit
Systems, Inc.
ICS8535-21
L
OW
S
KEW
, 1-
TO
-2
LVCMOS/LVTTL-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= 0C
TO
70C
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8535AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2004
6
Integrated
Circuit
Systems, Inc.
ICS8535-21
L
OW
S
KEW
, 1-
TO
-2
LVCMOS/LVTTL-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
A
DDITIVE
P
HASE
J
ITTER
Input/Output Additive Phase Jitter,
Integration Range: 12KHz - 20MHz at
156.25MHz = 0.03ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the fun-
damental compared to the power of the fundamental is called
the
dBc Phase Noise. This value is normally expressed using
a Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the
fundamental frequency to the power value of the fundamental.
This ratio is expressed in decibels (dBm) or a ratio of the power
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher
than the noise floor of the device. This is illustrated above. The
in the 1Hz band to the power in the fundamental. When the
required offset is specified, the phase noise is called a
dBc
value, which simply means dBm at a specified offset from the
fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired ap-
plication over the entire time record of the signal. It is math-
ematically possible to calculate an expected bit error rate given
a phase noise plot.
device meets the noise floor of what is shown, but can actually
be lower. The phase noise is dependant on the input source
and measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dB
c
/
H
Z
8535AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2004
7
Integrated
Circuit
Systems, Inc.
ICS8535-21
L
OW
S
KEW
, 1-
TO
-2
LVCMOS/LVTTL-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ROPAGATION
D
ELAY
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
S
KEW
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.165V
t
sk(o)
nQx
Qx
nQy
Qy
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
Q0, Q1
nQ0, nQ1
t
PD
CLK0,
CLK1
tsk(pp)
nQx
Qx
nQy
Qy
PART 1
PART 2
P
ART
-
TO
-P
ART
S
KEW
Q0, Q1
nQ0, nQ1
V
CC
V
EE
8535AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2004
8
Integrated
Circuit
Systems, Inc.
ICS8535-21
L
OW
S
KEW
, 1-
TO
-2
LVCMOS/LVTTL-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended that the
board designers simulate to guarantee compatibility across all
printed circuit and clock component process variations.
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
T
ERMINATION
FOR
LVPECL O
UTPUTS
8535AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2004
9
Integrated
Circuit
Systems, Inc.
ICS8535-21
L
OW
S
KEW
, 1-
TO
-2
LVCMOS/LVTTL-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
S
CHEMATIC
E
XAMPLE
Figure 3 shows a schematic example of the ICS8535-21. The
decoupling capacitors should be physically located near the
power pin. For ICS8535-21, the unused clock outputs can be
left floating.
F
IGURE
3. ICS8535-21 LVPECL B
UFFER
S
CHEMATIC
E
XAMPLE
VCC
R5
82.5
R3
50
+
-
CLK0
C1
10uf
Optional Termination
R4
133
(U1-14)
R2
50
Zo = 50
R7
82.5
Zo = 50
CLK1
C2
.1uF
Zo = 50
(U1-8)
Vcco = 3.3V
VCC = 3.3V
R1
50
CLK_EN
(U1-7)
Zo = 50
C4
.1uF
R6
133
CLK_SEL
+
-
U2
8535-21
1
2
3
4
5
6
11
8
9
10
12
14
13
7
VEE
CLK_EN
CLK_SEL
CLK0
VEE
CLK1
nc
VCC
nQ1
Q1
nQ0
VCC
Q0
VCC
C3
.1uF
8535AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2004
10
Integrated
Circuit
Systems, Inc.
ICS8535-21
L
OW
S
KEW
, 1-
TO
-2
LVCMOS/LVTTL-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8535-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8535-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 50mA = 173.25mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 x 30mW = 60mW
Total Power
_MAX
(3.465V, with all outputs switching) = 173.25mW + 60mW = 233.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 85.5C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.233W * 85.5C/W = 90C. This is well below the limit of 125C.
This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are loaded, supply
voltage, air flow, and the type of board (single layer or multi-layer).
JA
by Velocity (Linear Feet per Minute)
T
ABLE
6. T
HERMAL
R
ESISTANCE
JA
FOR
14-
PIN
TSSOP, F
ORCED
C
ONVECTION
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
146.4C/W
125.2C/W
112.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
93.2C/W
85.5C/W
81.2C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8535AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2004
11
Integrated
Circuit
Systems, Inc.
ICS8535-21
L
OW
S
KEW
, 1-
TO
-2
LVCMOS/LVTTL-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 4.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a
termination voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
0.9V
(V
CC_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CC_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
4. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
8535AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2004
12
Integrated
Circuit
Systems, Inc.
ICS8535-21
L
OW
S
KEW
, 1-
TO
-2
LVCMOS/LVTTL-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8535-21 is: 412
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
14 L
EAD
TSSOP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
146.4C/W
125.2C/W
112.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
93.2C/W
85.5C/W
81.2C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8535AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2004
13
Integrated
Circuit
Systems, Inc.
ICS8535-21
L
OW
S
KEW
, 1-
TO
-2
LVCMOS/LVTTL-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
14 L
EAD
TSSOP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
R
EFERENCE
D
OCUMENT
: JEDEC P
UBLICATION
95, MO-153
L
O
B
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Y
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8535AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2004
14
Integrated
Circuit
Systems, Inc.
ICS8535-21
L
OW
S
KEW
, 1-
TO
-2
LVCMOS/LVTTL-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
9. O
RDERING
I
NFORMATION
<
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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