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85411AM
www.icst.com/products/hiperclocks.html
REV. B JUNE 16, 2004
1
Integrated
Circuit
Systems, Inc.
ICS85411
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS85411 is a low skew, high performance
1-to-2 Differential-to-LVDS Fanout Buffer and a
member of the HiPerClockSTM family of High
Perfor mance Clock Solutions from ICS. The
CLK, nCLK pair can accept most standard differ-
ential input levels.The ICS85411 is characterized to oper-
ate from a 3.3V power supply. Guaranteed output and
par t-to-par t skew character istics make the ICS85411
ideal for those clock distribution applications demand-
ing well defined perfor mance and repeatability.
F
EATURES
2 differential LVDS outputs
1 differential CLK, nCLK clock input
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 650MHz
Translates any single ended input signal to
LVDS levels with resistor bias on nCLK input
Output skew: 20ps (maximum)
Part-to-part skew: 250ps (maximum)
Additive phase jitter, RMS: 0.05ps (typical)
Propagation delay: 2.5 ns (maximum)
3.3V operating supply
0C to 70C ambient operating temperature
Lead-Free package available
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS85411
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
HiPerClockSTM
ICS
V
DD
CLK
nCLK
GND
8
7
6
5
Q0
nQ0
Q1
nQ1
CLK
nCLK
background image
85411AM
www.icst.com/products/hiperclocks.html
REV. B JUNE 16, 2004
2
Integrated
Circuit
Systems, Inc.
ICS85411
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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background image
85411AM
www.icst.com/products/hiperclocks.html
REV. B JUNE 16, 2004
3
Integrated
Circuit
Systems, Inc.
ICS85411
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
3B. D
IFFERENTIAL
DC C
HARACTERISTICS
,
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DD
= 3.3V5%, T
A
= 0C
TO
70C
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NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3C. LVDS DC C
HARACTERISTICS
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DD
= 3.3V5%, T
A
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AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
10mA
Surge Current
15mA
Package Thermal Impedance,
JA
112.7C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
background image
85411AM
www.icst.com/products/hiperclocks.html
REV. B JUNE 16, 2004
4
Integrated
Circuit
Systems, Inc.
ICS85411
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
T
ABLE
4. AC C
HARACTERISTICS
,
V
DD
= 3.3V5% T
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= 0C
TO
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85411AM
www.icst.com/products/hiperclocks.html
REV. B JUNE 16, 2004
5
Integrated
Circuit
Systems, Inc.
ICS85411
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
A
DDITIVE
P
HASE
J
ITTER
Input/Output Additive Phase Jitter
@ 200MHz (12KHz to 20MHz)
= 0.05ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
500M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dBc/H
Z

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