Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Clock Input Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- Differential DC Characteristics
- LVDS DC Characteristics
- AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Part-to-Part Skew Diagram
- Output Skew Diagram
- Bank Skew Diagram
- Output Rise/Fall Time Diagram
- odc & tPeriod Diagram
- Propagation Delay Diagram
- VOD Setup Diagram
- VOS Setup Diagram
- IOS Setup Diagram
- IOSD Setup Diagram
- IOFF Setup Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Single ended Signal Driving Differential Input Diagram
- Differential Clock Input Interface
- HiPerClockS CLK/nCLK Input Driven by ICS HiPerClockS LVHSTL Driver Diagram
- HiPerClockS CLK/nCLK Input Driven by 3.3V LVPECL Driver Diagrams
- HiPerClockS CLK/nCLK Input Driven by 3.3V LVPECL w/AC Couple Driver Diagrams
- LVDS Driver Termination
- Typical LVDS Driver Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
ICS8547AY
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 4, 2003
1
Integrated
Circuit
Systems, Inc.
HiPerClockSTM
,&6
4
8 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
Q4A
nQ4A
nQ4B
Q4B
nCLK4
CLK4
CLK5
nCLK5
Q5B
nQ5B
nQ5A
Q5A
Q2A
nQ2A
nQ2B
Q2B
nCLK2
CLK2
CLK1
nCLK1
Q1B
nQ1B
nQ1A
Q1A
V
DDO
GND
V
DD
Q0B
nQ0B
nQ0A
Q0A
nCLK0
CLK0
V
DD
GND
V
DDO
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8547
V
DDO
GND
V
DD
Q3B
nQ3B
nQ3A
Q3A
nCLK3
CLK3
V
DD
GND
V
DDO
CLK0
nCLK0
Q0A
nQ0A
Q0B
nQ0B
CLK1
nCLK1
Q1A
nQ1A
Q1B
nQ1B
CLK2
nCLK2
Q2A
nQ2A
Q2B
nQ2B
CLK3
nCLK3
Q3A
nQ3A
Q3B
nQ3B
CLK4
nCLK4
Q4A
nQ4A
Q4B
nQ4B
CLK5
nCLK5
Q5A
nQ5A
Q5B
nQ5B
ICS8547
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
B
UFFERS
G
ENERAL
D
ESCRIPTION
The ICS8547 is a Hex low skew, high perfor-
mance 1-to-2 Differential-to-LVDS Clock Buffer
and a member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. Utilizing
Low Voltage Differential Signaling (LVDS) the
ICS8547 provides a low power, low noise, point-to-point solu-
tion for distributing clock signals over controlled impedances
of 100
. The ICS8547 has six selectable clock inputs. The
CLKx, nCLKx pairs can accept any differential input levels
and translates them to 3.3V LVDS output levels.
Guaranteed output and part-to-part skew specifications make
the ICS8547 ideal for those applications demanding well
defined performance and repeatability.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
12 LVDS outputs
Selectable CLKx, nCLKx inputs
CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 700MHz
Translates any differential input signal (LVPECL, LVHSTL,
SSTL, DCM) to LVDS levels without external bias networks
Translates any single-ended input signal to LVDS
with resistor bias on nCLKx input
Output skew: 250ps (maximum)
Bank skew: 15ps (maximum)
Part-to-part skew: 500ps (maximum)
Propagation delay: 1.8ns (maximum)
3.3V operating supply
0C to 85C ambient operating temperature
Industrial temperature information available upon request
ICS8547AY
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 4, 2003
2
Integrated
Circuit
Systems, Inc.
ICS8547
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
B
UFFERS
T
ABLE
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ICS8547AY
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 4, 2003
3
Integrated
Circuit
Systems, Inc.
ICS8547
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
B
UFFERS
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3. C
LOCK
I
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ICS8547AY
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 4, 2003
4
Integrated
Circuit
Systems, Inc.
ICS8547
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
B
UFFERS
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= 0C
TO
85C
T
ABLE
4B. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= 0C
TO
85C
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= 0C
TO
85C
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1
A
m
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
ICS8547AY
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 4, 2003
5
Integrated
Circuit
Systems, Inc.
ICS8547
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
B
UFFERS
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= 0C
TO
85C
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ICS8547AY
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 4, 2003
6
Integrated
Circuit
Systems, Inc.
ICS8547
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
B
UFFERS
P
ARAMETER
M
EASUREMENT
I
NFORMATION
D
IFFERENTIAL
I
NPUT
L
EVEL
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVDS
3.3V5%
POWER SUPPLY
+
-
Float GND
3.3V
P
ART
-
TO
-P
ART
S
KEW
V
CMR
Cross Points
V
PP
GND
CLKx
nCLKx
V
DD
P
ROPAGATION
D
ELAY
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock Outputs
20%
80%
20%
80%
t
R
t
F
V
O D
tsk(o)
Qx
Qy
O
UTPUT
S
KEW
tsk(pp)
PART 1
PART 2
CLKx
t
PD
odc & t
P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
QxA, QxB
nCLKx
nQx
nQy
Qx
Qy
nQx
nQy
nQxA, nQxB
QxA, QxB
nQxA, nQxB
B
ANK
S
KEW
tsk(b)
QxA,
nQxA
QxA,
nQxA
QxB,
nQxB
QxB,
nQxB
ICS8547AY
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 4, 2003
7
Integrated
Circuit
Systems, Inc.
ICS8547
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
B
UFFERS
V
OS
/
D
VOS
S
ETUP
I
OFF
S
ETUP
I
OSD
S
ETUP
I
OS
S
ETUP
V
OD
/
D
VOD
S
ETUP
out
out
LVDS
DC Input
V
OS
/
V
OS
V
DD
100
out
out
LVDS
DC Input
V
OD
/
V
OD
V
DD
out
out
LVDS
DC Input
I
OSD
V
DD
out
LVDS
DC Input
I
OS
I
OSB
V
DD
out
LVDS
I
OFF
V
DD
ICS8547AY
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 4, 2003
8
Integrated
Circuit
Systems, Inc.
ICS8547
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
B
UFFERS
A
PPLICATION
I
NFORMATION
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
R2
1K
V
DD
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
ICS8547AY
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 4, 2003
9
Integrated
Circuit
Systems, Inc.
ICS8547
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
B
UFFERS
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 2 to 5 show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver com-
ponent to confirm the driver termination requirements. For ex-
ample in
Figure 2, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
F
IGURE
2. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
F
IGURE
3. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
F
IGURE
4. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
5. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
ICS8547AY
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 4, 2003
10
Integrated
Circuit
Systems, Inc.
ICS8547
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
B
UFFERS
T
RANSISTOR
C
OUNT
The transistor count for ICS8547 is: 1117
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
R
ELIABILITY
I
NFORMATION
Zo = 50
R1
100
3.3V
+
-
Zo = 50
LVDS_Driver
3.3V
F
IGURE
6. T
YPICAL
LVDS D
RIVER
T
ERMINATION
LVDS D
RIVER
T
ERMINATION
Figure 6 shows typical termination for LVDS driver in character-
istic impedance of 100
differential (50
single) transmission
line environment. For buffer with multiple LDVS driver, it is rec-
ommended to terminate the unused outputs.
ICS8547AY
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 4, 2003
11
Integrated
Circuit
Systems, Inc.
ICS8547
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
B
UFFERS
P
ACKAGE
O
UTLINE
- Y S
UFFIX
T
ABLE
6. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
N
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f
e
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0
5
.
5
e
C
I
S
A
B
0
5
.
0
L
5
4
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0
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.
0
5
7
.
0
q
0
-
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7
c
c
c
-
-
-
-
8
0
.
0
ICS8547AY
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 4, 2003
12
Integrated
Circuit
Systems, Inc.
ICS8547
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
B
UFFERS
T
ABLE
7. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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