Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Input Function Tables
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Cycle-to-Cycle Jitter Diagram
- Output Skew Diagram
- odc & tPeriod Diagram
- Output Rise/Fall Time Diagram
- Static Phase Offset Diagram
- Propagation Delay Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Single Ended Signal Driving Differential Input Diagram
- Power Supply Filtering Techniques
- Power Supply Filtering Diagram
- Differential Clock Input Interface
- HiPerClockS CLK/nCLK Input Driven by ICS HiPerClockS LVHSTL Driver Diagram
- HiPerClockS CLK/nCLK Input Driven by 3.3V LVPECL Driver Diagrams
- HiPerClockS CLK/nCLK Input Driven by 3.3V LVDS Driver Diagrams
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
8602BY
www.icst.com/products/hiperclocks.html
REV. F APRIL 16, 2003
1
Integrated
Circuit
Systems, Inc.
ICS8602
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS8602 is a high performance, low skew,
1-to-9 Differential-to-LVCMOS/LVTTL Zero De-
lay Buffer and a member of the HiPerClockSTM
family of High Performance Clocks Solutions
from ICS. The CLK, nCLK pair can accept most
standard differential input levels. The VCO operates at a fre-
quency range of 250MHz to 500MHz. The external feedback
allows the device to achieve "zero delay" between the input
clock and the output clocks. The device is designed only for
1:1 input/output frequency ratios. The output divider allows a
wide input/output frequency range with the 250MHz to
500MHz VCO. The PLL_SEL pin can be used to bypass the
PLL for system test and debug purposes. In bypass mode,
the reference clock is routed around the PLL and into the in-
ternal output dividers.The low impedance LVCMOS/LVTTL out-
puts are designed to drive 50
series or parallel terminated
transmission lines. The effective fanout can be doubled by
utilizing the ability of the outputs to drive two series termi-
nated lines. The differential reference clock input will accept
any differential signal levels.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Fully integrated PLL
9 LVCMOS/LVTTL outputs, 7
typical output impedance
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 15.625MHz to 250MHz
Input frequency range: 15.625MHz to 250MHz
VCO range: 250MHz to 500MHz
External feedback for "zero delay" clock regeneration
with configurable frequencies
Cycle-to-cycle jitter: 36ps (typical)
Output skew: 125ps (maximum)
Static Phase Offset: TBD100ps (typical)
3.3V supply voltage
0C to 70C ambient operating temperature
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
DDO
Q5
GND
Q4
V
DDO
Q3
GND
MR/nOE
V
DDA
V
DD
CLK
nCLK
GND
DIV_SEL0
DIV_SEL1
GND
GND
Q2
V
DDO
Q1
GND
Q0
V
DDO
FB_IN
GND
Q6
V
DDO
Q7
GND
Q8
V
DDO
PLL_SEL
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8602
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
HiPerClockSTM
,&6
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
SEL0
SEL1
CLK
nCLK
FB_IN
PLL_SEL
MR/nOE
0
1
PLL
2
4
8
16
8602BY
www.icst.com/products/hiperclocks.html
REV. F APRIL 16, 2003
2
Integrated
Circuit
Systems, Inc.
ICS8602
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
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T
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3B. C
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F
UNCTION
T
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, PLL_SEL = 0
PLL B
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8602BY
www.icst.com/products/hiperclocks.html
REV. F APRIL 16, 2003
3
Integrated
Circuit
Systems, Inc.
ICS8602
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
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D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
0
4
A
m
I
A
D
D
t
n
e
r
r
u
C
y
l
p
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o
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n
A
0
1
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m
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t
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r
r
u
C
y
l
p
p
u
S
t
u
p
t
u
O
0
6
1
A
m
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
42.1C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
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r
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m
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V
D
D
V
=
N
I
V
5
6
4
.
3
=
0
5
1
A
K
L
C
n
V
D
D
V
=
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V
5
6
4
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3
=
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M
C
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T
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g
a
t
l
o
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t
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p
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n
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m
m
o
C
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+
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N
G
V
D
D
5
8
.
0
-
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V
s
a
d
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n
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f
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s
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t
l
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v
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n
o
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m
o
C
:
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E
T
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N
H
I
.
s
i
K
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C
n
,
K
L
C
r
o
f
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a
t
l
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u
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x
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c
il
p
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n
e
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l
g
n
i
s
r
o
F
:
2
E
T
O
N
V
D
D
.
V
3
.
0
+
8602BY
www.icst.com/products/hiperclocks.html
REV. F APRIL 16, 2003
4
Integrated
Circuit
Systems, Inc.
ICS8602
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
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m
a
r
a
P
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n
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h
g
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-
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w
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z
H
M
0
,
V
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=
L
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f
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D
B
T
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B
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s
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)
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f
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,
z
H
M
3
3
1
=
F
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R
f
,
V
3
.
3
=
L
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S
_
L
L
P
z
H
M
6
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2
=
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C
V
f
0
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1
D
B
T
s
p
,
z
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=
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f
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V
3
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=
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f
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:
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T
O
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t
a
d
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r
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5
6
d
r
a
d
n
a
t
S
C
E
D
E
J
h
t
i
w
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c
n
a
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r
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:
4
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T
O
N
8602BY
www.icst.com/products/hiperclocks.html
REV. F APRIL 16, 2003
5
Integrated
Circuit
Systems, Inc.
ICS8602
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
D
IFFERENTIAL
I
NPUT
L
EVEL
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
V
DD
,
V
DDA
,
V
DDO
= 1.65V5%
GND = -1.65V5%
C
YCLE
-
TO
-C
YCLE
J
ITTER
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
V
DD
odc & t
P
ERIOD
P
ROPAGATION
D
ELAY
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock Outputs
20%
80%
80%
20%
t
R
t
F
tsk(o)
V
DDO
2
V
DDO
2
Qx
Qy
O
UTPUT
S
KEW
nCLK
CLK
Q0:Q8
t
PD
V
DDO
2
S
TATIC
P
HASE
O
FFSET
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
Q0:Q8
V
DDO
2
V
DDO
2
V
DDO
2
Q0:Q8
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
t()
V
DD
2
(where
t() is any random sample, and t ()
mean
is the average
of the sampled cycles measured on controlled edges)
t()
mean
= Static Phase Offset
nCLK
FB_IN
CLK
8602BY
www.icst.com/products/hiperclocks.html
REV. F APRIL 16, 2003
6
Integrated
Circuit
Systems, Inc.
ICS8602
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
PRELIMINARY
A
PPLICATION
I
NFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8602 provides sepa-
r a t e p o w e r s u p p l i e s t o i s o l a t e a n y h i g h s w i t c h i n g
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2 illustrates how
a 10
resistor along with a 10
F and a .01
F bypass
capacitor should be connected to each V
DDA
pin.
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
8602BY
www.icst.com/products/hiperclocks.html
REV. F APRIL 16, 2003
7
Integrated
Circuit
Systems, Inc.
ICS8602
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
PRELIMINARY
F
IGURE
3C. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3B. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3D. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 3A to 3D show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
3A. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
8602BY
www.icst.com/products/hiperclocks.html
REV. F APRIL 16, 2003
8
Integrated
Circuit
Systems, Inc.
ICS8602
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8602 is: 1828
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8602BY
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REV. F APRIL 16, 2003
9
Integrated
Circuit
Systems, Inc.
ICS8602
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
PRELIMINARY
P
ACKAGE
O
UTLINE
- Y S
UFFIX
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
3
A
-
-
-
-
0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
9
0
.
0
-
-
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
.
f
e
R
0
6
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
.
f
e
R
0
6
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5
e
C
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S
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B
0
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.
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5
4
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0
6
.
0
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.
0
q
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www.icst.com/products/hiperclocks.html
REV. F APRIL 16, 2003
10
Integrated
Circuit
Systems, Inc.
ICS8602
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ELAY
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ENERATOR
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ABLE
8. O
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While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
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